# Optimizing Carry-Skip Adders for Minimal Delay

• MHB
• evinda
In summary, the conversation discusses the use of a binary adder carry-skip with 32 bits, where the individual adders have varying sizes and the skip is not done at the first and last adder. The problem is to determine the optimal size for each individual adder to minimize the mean time of computing the output carry, taking into account the delays caused by full adder circuits and multiplexers. The formula for optimal size is suggested to be $m=\sqrt{\frac n2}$, but it does not consider the specific delays mentioned in the problem statement. A suggestion is made to draw a diagram and optimize the formula for the desired mean time.
evinda
Gold Member
MHB
Hello! (Wave)

Let a binary adder carry-skip of $32$ bits, at which the size of the individual adders is not necessarily the same. Suppose that the individual adders are adders spreading carry, and that the skip is not done at the first and at the last individual adder. If we can use 4 individual adders, and the available sizes of adders are 4, 8 and 12 bits, compute the size that each individual adder should have, so that the mean time of the computation of the output carry is minimized, supposing that each circuit of a full adder of 1 bit and each circuit of a multiplexer bring a delay of $2T$ at the computation, while the gates AND of 4,8 and 12 inputs bring a delay of $T, 2T$ and $2T$, respectively, where $T$ is the time of delay of an elementary gate.

Could you give me a hint? :unsure:

Hey evinda!

I'm not all that familiar with carry-skip adders yet, and what their mean time of the computation of the output carry is.
Do you have a formula for that? (Wondering)
And maybe a diagram as an example? (Wondering)

I did find on wiki that the optimal size for the carry-skip adders is $m=\sqrt{\frac n2}$, where $n$ is the total number of bits, and $m$ is the bits of each adder.
So the size of the adders for this problem is probably around $m=\sqrt{\frac {32}2}=4$. That is 8 adders of size 4. :unsure:

Klaas van Aarsen said:
I did find on wiki that the optimal size for the carry-skip adders is $m=\sqrt{\frac n2}$, where $n$ is the total number of bits, and $m$ is the bits of each adder.
So the size of the adders for this problem is probably around $m=\sqrt{\frac {32}2}=4$. That is 8 adders of size 4. :unsure:

At this size is the delay taken into consideration?

Do we have to do that for each available adder? (Thinking)

evinda said:
At this size is the delay taken into consideration?
The delays as mentioned in the problem statement have not been taken into account.
Instead it is a formula I found on wiki that makes certain assumptions about the delays.
It also doesn't say how it was optimized, which may be different from the problem statement. :unsure:

evinda said:
Do we have to do that for each available adder?
I think we have to draw a diagram of a couple of adders together, identify where and what the delays are exactly, find the formula for the desired mean, and optimize that formula to be minimal. (Sweating)

## 1. How does optimizing carry-skip adders improve their performance?

Optimizing carry-skip adders involves reducing the propagation delay of the adder circuit, allowing for faster operation and improved performance.

## 2. What is the main factor that affects the delay of carry-skip adders?

The main factor that affects the delay of carry-skip adders is the length of the carry chain, which is the number of adder stages in the circuit.

## 4. How do carry-skip adders compare to other types of adders in terms of delay?

Carry-skip adders typically have a lower delay compared to ripple-carry adders, but may have a higher delay compared to carry-select or carry-lookahead adders.

## 5. Are there any trade-offs to consider when optimizing carry-skip adders for minimal delay?

Yes, optimizing for minimal delay may result in a larger circuit size, increased power consumption, or more complex design techniques, so it is important to consider these trade-offs when choosing an optimization strategy.

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