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evinda

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Let a binary adder carry-skip of $32$ bits, at which the size of the individual adders is not necessarily the same. Suppose that the individual adders are adders spreading carry, and that the skip is not done at the first and at the last individual adder. If we can use 4 individual adders, and the available sizes of adders are 4, 8 and 12 bits, compute the size that each individual adder should have, so that the mean time of the computation of the output carry is minimized, supposing that each circuit of a full adder of 1 bit and each circuit of a multiplexer bring a delay of $2T$ at the computation, while the gates AND of 4,8 and 12 inputs bring a delay of $T, 2T$ and $2T$, respectively, where $T$ is the time of delay of an elementary gate.

Could you give me a hint? :unsure: