'Output Enable' switch using BJT or FET

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    Bjt Fet Switch
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The discussion focuses on designing an output enable circuit using BJT or FET for a digital application with specified voltage levels of 3.3V and 0V. The circuit should provide a high voltage output when disabled and allow for 5-10mA current when enabled, with a maximum frequency of 10KHz. Suggestions include using a PNP transistor with the emitter connected to Vcc and the collector to the logic gate output, controlled by a resistor at the base. It is important to verify if the logic gate can handle being pulled high when the output is low, potentially requiring an additional transistor for high impedance. Overall, the design aims to effectively manage output states in a digital logic context.
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How to design a Output enable ckt (like the ones in logic gates and buffers) using a simple component like BJT or FET.
 
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Can you supply some more details?

Is this an analog or digital circuit?
How high is the high voltage out and how low is the low voltage out?
What are the high and low voltage you want to use to enable or disable?
When disabled, do you want a high voltage, low voltage or just high impedance out?
When enabled, how much current do you need at the output?
What is the highest frequency that will be used?
 
Is this an analog or digital circuit?
>>digital
How high is the high voltage out and how low is the low voltage out?
>.3.3V and 0V
What are the high and low voltage you want to use to enable or disable?
>>3.3V and 0V
When disabled, do you want a high voltage, low voltage or just high impedance out?
>> high voltage
When enabled, how much current do you need at the output?
>> 5-10mA
What is the highest frequency that will be used?
>> max 10KHz
 
Have you considered using a pnp transistor with the emitter connected to Vcc, the collector connector connected to the logic gate output and the base connected through a resistor to be your enable control?
 
skeptic2 said:
Have you considered using a pnp transistor with the emitter connected to Vcc, the collector connector connected to the logic gate output and the base connected through a resistor to be your enable control?
Where do I get the output?
 
The output would still be the logic gate output. All the transistor does is pull the output pin high when not enabled. You will need to check the logic family to see if the gate can stand being pulled high when the output is low. If not, you will need another transistor between the output of the gate and the collector to become high impedance at the same time.
 
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