Well I had read somewhere that intel is developin a process which uses "extreme ultraviolet light photolithography tool" which will help make chips with an average feature size of 32 nanometers.Now even the atoms of silicon and the doping material occupy some space so they can't just go on decreasing the size of components on ICs.I mean there must be some limit to it.
So you've run across one of the limiting factors of constructing circuits on an IC,
photolithography, where the wavelength of light used, poses a limitation. The shorter the wavelength, the smaller the architecture that may be drawn on the mask.
You may want to look up "Moore's Law" & see how this applies to your topic.
I can get you started with an article; but since this is your presentation, I'll let you find the rest.
Pushing the limits of lithography for IC production. If you are an IEEE member you may be able to access on line otherwise take a look in your local college library.
Secondly, I had also read that as we try to increase the packing density the doping material starts to clump together so even this would put a limit on the minimum size of the components on the IC. I found only these two limitations coz of which sometime in the future the ICs will reach their max limit of development and then their will be stagnation.
So besides the imaging process, the IC construction (deposition & etching of material onto bulk silicon), also poses a limitation.
One general reference that I recommend is
Semiconductor Manufacturing.
During construction, dust contaminants in the fabrication area, initially posed no major concern, but as the architechture began to shrink, these particles did interfere with IC function and reliability and ways to reduce contaminants needed to be addressed. I don't know about clumping of atoms of the dopant, however this sounds like a deposition issue.
Other areas that you may want to look into.. Here is an excerpt of an eetimes article that discusses some additional limitations
Experts spar over limits of IC scaling.
Mark Bohr, an Intel senior fellow and director of process architecture...
"Besides scaling, there will be other major barriers going down the technology curve. ''Power density is the limiting factor,'' Bohr said. ''There will be less emphasis on frequency and a new emphasis on power efficiency.''
In addition, voltage barriers, velocity limitations and variability are becoming a concern going forward, said Hans Stork, senior vice president and chief technology officer at Texas Instruments Inc. ''The physics are working against us,'' Stork said. "
If u could point out something else which might be helpful then I would really be thankfulto u.And you could u xplain which methods r used to prevent the clumping of the atoms of the doping material.
