1. Not finding help here? Sign up for a free 30min tutor trial with Chegg Tutors
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Phase relationships in Thévenin circuit

  1. Dec 11, 2016 #1
    1. The problem statement, all variables and given/known data
    2014 Q2.png
    2. Relevant equations

    3. The attempt at a solution
    PhotoScan.jpg

    For part (c), should the phasor diagram just have everything on a straight line, save for the Rt and Vrt?

    Honestly not sure how to attempt part (d) as we never really covered phase relationships in lectures, just looking specifically at phase diagrams of a capacitor or inductor.
     
  2. jcsd
  3. Dec 11, 2016 #2

    cnh1995

    User Avatar
    Homework Helper

    It would be convenient if you chose the load voltage as the reference phasor in your phasor diagram. You can solve all the questions upto e) once you draw this phasor diagram.
    Start with the horizontal load voltage phasor VL∠0°.
     
    Last edited: Dec 11, 2016
  4. Dec 11, 2016 #3
    Ok. So will all the Voltages, save for the Thévenin resistance voltage, be on the horizontal axis? Or is VL shifted as result of the complex impedance of RT before it.
     
    Last edited: Dec 11, 2016
  5. Dec 11, 2016 #4
    Actually, after thinking about it some more, would the voltage of VL be VTH - VR given the voltage from VTH isn't 'dropped' across anything else other then those two resistances?
     
  6. Dec 11, 2016 #5

    cnh1995

    User Avatar
    Homework Helper

    You are forgetting the j0.25 ohm reactance. Yes, VL and VR will add algebraically since they are in phase but that won't give you Vth. You need to draw the reactance drop phasor too.
     
  7. Dec 12, 2016 #6
    Ok, I am still not sure how the phasor diagram should look. Prior to this, the only phasor diagrams we have been taught is the general one for a capacitor and inductor.

    Would it look like this?

    PhotoScan.jpg
     
  8. Dec 12, 2016 #7

    cnh1995

    User Avatar
    Homework Helper

    No. Vth and VL are not in phase. VR and VL are in phase. Recall KVL. Sum of the voltage drops across Thevenin resistance, Thevenin reactance and load is equal to the Thevenin voltage. You know the magnitudes of three of them and their phase relation.

    Edit: Just to confirm, are we using the same terminology? I am taking VR as the voltage across the thevenin resistance, VL as the voltage across the storage heater load and Vth is the mains voltage.
     
  9. Dec 12, 2016 #8
    Ok, that's what I meant when I said
    I was taking VR to be the voltage drop for both the reactance and resistance.

    Would the phasor diagram look like this then?

    PhotoScan.jpg
     
  10. Dec 12, 2016 #9

    cnh1995

    User Avatar
    Homework Helper

    Ok. Let's call it the Thevenin impedance drop Vz.
    In your diagram, you have shown Vz leading Vth by 45°, which is not true. Phase difference between Vz and Vth is not 45°. You need to show the Thevenin reactance drop Vx too in the diagram (drop across the line reactance).
    Start with the horizontal load voltage phasor VL. How will Thevenin resistance drop VR and Thevenin reactance drop Vx be added to VL? You know the magnitudes of these three and their phase relationship. You also know that their phasor addition will give you Vth. Could you proceed with this?
     
    Last edited: Dec 12, 2016
  11. Dec 12, 2016 #10
    Ok. There's been confusion from terminology, so I'll use yours (Vth, Vr, Vx,VL)

    Right. So Vth = Vr + Vx + VL

    The current in the circuit is 80A

    This means Vr = 80(0.25) = 25

    And Vx 80(j0.25) = j25

    VL = Vth - Vr - Vx
    VL = (240 +j0) - 25 - j25
    VL = 215 - j25

    Is this right so far?
     
  12. Dec 12, 2016 #11

    cnh1995

    User Avatar
    Homework Helper

    20 and j20...
    We are taking VL as reference here.
    So, Vth= (VL+j0)+20+j20.
    i.e.
    Vth=(VL+20)+j20.

    Can you draw the phasor diagram from this green equation?
     
  13. Dec 12, 2016 #12
    Sorry, do know what I was thinking there :sorry:

    I'm not sure. Do I take the VL and the 20(Vr) both to be on the horizontal axis and just put j20(Vx on the Vertical axis?

    Where do I draw Vth?
     
  14. Dec 12, 2016 #13

    cnh1995

    User Avatar
    Homework Helper

    Exactly. The reactance drop j20 will be vertical, on the tip of the horizontal phasor (VL+20). It is in quadrature with the resistive drop.
    Vth is the "phasor addition" of voltages on horizontal and vertical axes. Don't they form a right angled triangle? Vth is its hypotenuse. You know the magnitude of the hypotenuse and the vertical side. You can compute the length of the horizontal side and get the load voltage.
     
  15. Dec 12, 2016 #14
    So, is this it?
    PhotoScan.jpg
     
  16. Dec 12, 2016 #15

    cnh1995

    User Avatar
    Homework Helper

    Your calculations are all correct, but in your phasor diagram, you should swap Vr and VL since you have assumed VL as the reference phasor. It's a standard practice to draw the reference phasor first and then draw the remaining ones.
     
  17. Dec 12, 2016 #16
    Ok. I'll do that in future. Can I draw the circuit currents in the diagram also? Is the 80A just along the VL?
     
  18. Dec 12, 2016 #17

    cnh1995

    User Avatar
    Homework Helper

    Yes.
     
  19. Dec 12, 2016 #18
    Ok, so for part (d) Calculate the phase relationship between the Thevenin equivalent circuit voltage and the current

    Do I work out the angle the current is lagging by?
     
  20. Dec 12, 2016 #19

    cnh1995

    User Avatar
    Homework Helper

    Yes. You can do it using elementary trigonometry.
     
  21. Dec 12, 2016 #20
    Grand. So it is:

    ϕ = sin-1(20/240) ≈ 4.78°.

    I take it for part(e) Calculate the total resistance of the storage heaters, it is:
    V/I

    VL / 80∠4.78°?
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted