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Practical Voltage Translator Question

  1. Sep 19, 2007 #1
    If logic levels of two chips do not match up, say a CPU at 3 volts and a peripheral at 5V, you will need to translate voltages. I want to do this for a serial interface, but I don't know if the translator will ruin my data. The serial signal is in the hundreds of MHz. The only thing to tell me what speed these translators can operate at in datasheets that I see are their propagation delays, which are about 5-9 ns. So how can I know if this delay will ruin my data. Say the data is non stop, with no rests. Will the delays add up to where I can't get all of the data through? Say the data is at 500MHz, so that is 2ns period for a pulse, which is well below 5-9ns. This makes me think it will not work. Can anyone give me some help?
  2. jcsd
  3. Sep 19, 2007 #2


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    A dc-dc converter will not pass data at this rate, it is designed specifically to smooth the output voltage so as not to pass ripples. The obvious solution would be to use an op-amp or there are probably CMOS HCT series gates that will switch on a 3v logic level and drive a 5v output.
  4. Sep 19, 2007 #3
    Well I'm looking at this part from TI http://focus.ti.com/docs/prod/folders/print/sn74lvc4245a.html

    This is for data signals, not as a power voltage regulator, so I don't think I'd ever try to use a dc-dc converter.

    This chip was designed specifically for what I'm trying to do, which is switch the voltage levels of a data bus. I can't really do this in an opamp, where I have bidirectional signals in some cases.

    I know there are some logic gates with almost no propagation delay, but I'm asking if a propagation delay of 5-9ns, which is the case for some of these translators, is going to interfere with a constant stream of data running in the hundreds of MHz.
  5. Sep 19, 2007 #4


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    I hadn't heard the term voltage translator so I thought you were looking at a dc-dc converter. This chip looks like it was made for the job, it's probably just sets of opamps internally hence the propagation delay.
    If the propogation delay is just a delay it shouldn't matter since it will affect all the bits the same, but if it blocks the input for that delay then you will have a reduced bandwidth. What does the spec say about max bandwidth.
  6. Sep 19, 2007 #5
    that's the problem, I don't see anything about bandwidth,data rate, frequency, etc. mentioned in the datasheet >.<

    I'd like to think it can operate at such high data rates, but I have no numbers to work with except propagation delay, and I'm not quite sure if that is a valid parameter to calculate a maximum data rate with.

    Thanks for your responses, I appreciate your input.
  7. Sep 19, 2007 #6


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    That chip will not be useful for signals in the 100s of MHz. What signals are you working with? I've never heard of bidirectional, multiple 100MHz signals. At those speeds, you use terminated differential transmission line techniques, not 5V logic or 3V logic.

    Can you be more specific about the application, the source of the signals, and what you want to do with them?
  8. Sep 19, 2007 #7
    ok, can I ask you why it would not work? Maybe some kind of calculation? Regardless of what it's used for, I would like to know how propagation delay relates to bandwidth, or maybe some other parameter you know of??

    I would like to use it on a memory bus, on a SPI serial interface, and some other stuff maybe.
    The memory bus is at 100MHz, the SPI i think is less, maybe 13MHz???
  9. Sep 19, 2007 #8
    p.s. I ask these questions because I want to understand. I'm not trying to challenge anyone or sound smart.
  10. Sep 19, 2007 #9


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    The key parameter that is missing from the datasheet is the Tw shown in the waveform diagrams, but not given in the tables, as far as I can see. That is the pulse width of the data, and if they specified a minimum Tw, that would be a first clue for how fast the datastream could be. They also don't specify a rise and fall time for the output driver, and that is another thing that you could use to tell you more about the maximum throughput bandwidth. You would especially need to know the tolerance on the rise time versus the fall time, to calculate what kind of data skew could result for fast signals going through the device.

    Based on the prop times tplh, tphl, etc., this does not appear to be a fast enough device to run several 100MHz. Maybe it could handle 100MHz, but I'm skeptical about that.

    SPI serial bus and a memory bus have different requirements. SPI signals are uni-directional (as long as you are keeping MOSI and MISO separate), so you don't need bidirectional level translation. And keep in mind that as long as your 5V device has "TTL compatible inputs", and your 3V device has "5V tolerant inputs", no level translators are needed (Quiz Question -- Why?).

    An external memory interface has uni-directional address lines, and a bi-directional shared data bus, so yes, the data bus translators would need to be bidirectional devices like the one you list. However, most 5V external memory devices like RAMS and Flash memory chips have TTL compatible inputs, and some 3V uPs have 5V tolerant inputs, so again, no translators are required. And sure as heck if you are going to try to run up near 100MHz in the external memory circuit, you are going to have to be extremely careful about layout, terminations, etc., and you are also going to use memory devices that are compatible with the uP without the need for voltage translation.

    Here is an old application note that I helped write many years ago, talking about the external memory interface timing considerations for a simple 8-bit uC. It will start to get you thinking about what timing considerations determine how fast you can run an external memory interface, and how logic decode delays affect that max speed:


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