Question about NOR gates and overflow

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To develop a minimal NOR circuit for detecting overflow using the sign bits of two addends (A and B) and their sum (S), it is essential to focus on the most significant bits (MSB) of these inputs. The overflow occurs when the MSB of A and B are the same, but the MSB of the sum S differs from them. Generalizing this for n-bit addends involves examining only the MSB, which simplifies the design. Designating one input as 'carry in' can also aid in determining overflow conditions. Understanding these principles allows for the effective creation of a NOR circuit tailored for overflow detection.
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How do I develop a minimal NOR circuit that detects overflow by examining the sign bits of two addends (A and B) and their sum (S)?

Doesn't this depend on how long the addends A and B are? Is there anyway I can generalize the result to n bit addends?

or perhaps I can just designate one input as 'the carry in', compare the MSB of the two addends and go from there?
 
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I believe the problem requires you to consider only the MSB of A and B, and the sum S of these bits. What are the overflow conditions given these 3 inputs? Work it out from there.
 
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