Robotics Project: Interfacing LCD Screen to FPGA

[Feldoh]

Hello,

I'm working on a robotics project with one of my friends for an (relatively small) competition at my school. Anyways part of our project involves interfacing an LCD screen to an FPGA however we're having a problem with that particular aspect of the design.

The clock signal on our FPGA is 50MHz and the optimal frequency of the LCD is 9MHz. Needless to say I'm rather confused on how to slow down the signal enough to meet spec for the LCD.

Spec is 7.83-9.26MHz with 9.00MHz ideal with a duty cycle of 50% +/- 5%

We can't seem to get a divider that will work, any suggestions?

 

[schip666!]

A multiple-stage counter should be able to divide by 6 to give you 8.3 MHz. I'm not sure which parts run at 50MHz these days though...

 

[Feldoh]

Thanks for the reply, I'll look into a multi-stage counter.

The board we're using is in the Altera Cyclone III family with an onboard crystal quartz oscillator at 50MHz.

 

[vk6kro]

Dividing from 50 MHz is not trivial and some families of chips do not work at this frequency.

You could just look for an 8 MHz crystal oscillator.

You can probably find a source near where you live, but here is one in West Australia:
http://members.iinet.net.au/~worcom/
Use the online catalog. Price is AU$4.40 plus post.

These usually just require +5 volts and ground, and you take the output from one of the 4 pins.

 

[Bob S]

If you just program a chip to divide by 6, you most likely will not get a 50% duty cycle. You may need to divide by 3 followed by a separate divide by 2 circuit.

Bob S

 

[vk6kro]

If you just program a chip to divide by 6, you most likely will not get a 50% duty cycle. You may need to divide by 3 followed by a separate divide by 2 circuit.

Bob S

Agreed.

One really useful trick to get a perfect 50 % duty cycle is to use a shift register. A 74F164 serial in, parallel out shift register is ideal and there are 74HC164 and other types available, depending on the input frequency required.

You feed in the 50 MHz, in this case, to the clock input then invert one of the outputs (with a 74F04 or similar high speed inverter) to feed this to the data input line.

Initially all outputs will be zeros, so these are fed back as ones by the inverter. However it takes 3 clock pulses for the 3rd output to go high, so the 4th clock pulse puts a zero from the data input line into the shift register first stage.

The process continues with each 3 input pulses producing high outputs and the next 3 producing low outputs.
So, you divide by 6 with a perfect 50% duty cycle.
The outputs of the shift register can be used to produce divisions of 2, 4, 6, 8, 10, 12, 14 and 16, just by moving the input connection of the inverter. Very useful for some oddball divisions.
Here is my circuit, which I developed years ago, but have not published (until now):
[PLAIN]http://dl.dropbox.com/u/4222062/Shift%20register%20idvider.PNG

It uses a NAND gate as an inverter. Artwork by John, VK6JY.

 

[Feldoh]

If you just program a chip to divide by 6, you most likely will not get a 50% duty cycle. You may need to divide by 3 followed by a separate divide by 2 circuit.

Bob S

That's the problem I'm having is that with a regular counter the duty cycle is too skewed.

Agreed.

One really useful trick to get a perfect 50 % duty cycle is to use a shift register. A 74F164 serial in, parallel out shift register is ideal and there are 74HC164 and other types available, depending on the input frequency required.

You feed in the 50 MHz, in this case, to the clock input then invert one of the outputs (with a 74F04 or similar high speed inverter) to feed this to the data input line.

Initially all outputs will be zeros, so these are fed back as ones by the inverter. However it takes 3 clock pulses for the 3rd output to go high, so the 4th clock pulse puts a zero from the data input line into the shift register first stage.

The process continues with each 3 input pulses producing high outputs and the next 3 producing low outputs.
So, you divide by 6 with a perfect 50% duty cycle.
The outputs of the shift register can be used to produce divisions of 2, 4, 6, 8, 10, 12, 14 and 16, just by moving the input connection of the inverter. Very useful for some oddball divisions.
Here is my circuit, which I developed years ago, but have not published (until now):

Thanks for the incite!