I hope you tried to understand my Theory of Operation. Please learn to state what you understand with a question so we can see where the correction is needed.
Here I will show 3 different types of "Astable Oscillators all using the same RC=T values but slightly different frequencies. These are all reliable methods with advantages and disadvantages. since your circuit is the 3rd, I put it's CMOS Logic equivalent which have a nominal 1/3 to 2/3 Vdd hysteresis thresholds from internal positive feedback ratios like your 22k/(100k+22k) = 18% of ideal output swings (Vcc-Vee).
Starting from the right, the +ve input toggles back and forth a ratio of the output, while the -ve input ramps towards that inverted threshold then flips when the inputs are equal. The 2nd circuit using CMOS Schmitt Inverter does the same except the ratios are internal between Vdd and Vss. The transition always occurs when the inputs are equal.
Now my 1st osc. differentiates the output but still has positive feedback for AC using two standard CMOS inverters. The Schottky diode pair can be left out if its input resistor limits the input switched current < 0.1 mA from over-voltage as the internal ESD clamp diodes will protect the device. So the 1st left resistor is just an arbitrary current limiter value then RC which differentiates the output instead of integrating it. In this case the threshold to reach is nom. 50% of Vdd on the left-most input.As always in
Falstad browser simulation, you can stop the simulation or speed it up, while a mouse thumbwheel can change any RLC value (or manual edit) so you can see how the time constant changes with RC=T towards the target threshold changes the "half-cycle time" of the repetition rate or frequency which is included in my plots. You can use the mouse wheel like a "pot" or select part > Slider> value= min, max. Each plots will show the max voltage on display by default, then I added more info > properties> >show info> .
Notice that the Op Amp needs a bipolar supply for a ground reference on Vin+_. To use a single supply, you would need an equal pull-up (Vdd) an pull-down (0v) to set the midpoint equal to the average output in order to get exactly 50% duty cycle.
If you consider the voltage drop across the resistor V=IR and the same current in the capacitor Ic=CdV/dt you get the exponential decay towards the driving voltage, which for low hysteresis looks is a fairly linear triangle. Then integration of the triangle with a LPF attenuates the odd harmonics again towards a fairly clean sine wave with harmonics not visible on a linear scale but quite visible on a dB scale such as a spectrum analyzer.
Simulation