Simulating a NAND/AND gate in Emitter Coupled Logic?

AI Thread Summary
The discussion focuses on simulating an AND/NAND gate using Emitter Coupled Logic (ECL), which is typically used for OR/NOR gates. Participants highlight the challenge of determining appropriate bias voltages (VBB1, VBB2) for the circuit to function correctly. It is noted that VBB should be set to the midpoint between the logic "0" and "1" voltage levels, with specific voltage ranges referenced from an ECL document. The conversation also touches on the differences in voltage calculations for NAND versus NOR configurations, emphasizing the use of a differential amplifier approach. Understanding these voltage settings is crucial for successfully implementing the NAND gate in ECL.
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Homework Statement


I need to simulate a AND/NAND gate with Emitter Coupled Logic. As I'm sure that most of you know, ECL is mostly used to make OR/NOR gates, so finding out how to make a NAND/AND gate is not as easy as it sounds.


Homework Equations





The Attempt at a Solution



I attached an image of a possible model that I found online. However, how do I know which values I should put in order to make the circuit work? How do I know which voltages should be in VBB1, VBB2, etc?

Thanks
 

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jean28 said:
How do I know which voltages should be in VBB1, VBB2
I did a web search and VBB is the bias voltage use to determine if an input is "true" or "false", but I couldn't find the specific voltages.
 
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jean28 said:
That is for OR/NOR functions.
True, but it does show that VBB for Q3 is -1.29V, while VCC is -5.2V, the same as your AND / NAND circuit. In general, VBB is set to the middle of the .8 voltage difference beween a logic "0" and a logic "1". I found an ECL document that specifies the voltage range for VBB as well as the other voltage ranges:

https://smartech.gatech.edu/jspui/bitstream/1853/32110/1/PG_TR_050518_RJP.pdf
 
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I think it will be slightly different for the NAND because if you follow the path from INB to VBB2 there is an aditional Vbe compared to a NOR. It goes...

INA - Vbe -Vbe +Vbe = VBB2

So set INA to mid way between logic 1 and 0 and you can calculate VBB2.

For INB it's..

INB - Vbe + Vbe = VBB1

Basically the principle is that of a differential amp/long tailed pair configured as a comparator (eg one input fixed voltage).

http://en.wikipedia.org/wiki/Differential_amplifier
 
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