Solving Race Condition in D-type Flip-Flops for 4 Output Loop

  • Thread starter Thread starter Dr-NiKoN
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AI Thread Summary
The discussion focuses on creating a circuit with four outputs that sequentially activate one at a time with each pulse, but the user encountered race-condition errors in their D-type flip-flop. The issue stemmed from incorrectly using a latch as a flip-flop, which led to the race conditions. After troubleshooting, the user resolved the problem and successfully implemented the desired functionality. The conversation highlights the importance of using the correct components in digital circuit design to avoid timing issues. Proper understanding of flip-flops and latches is crucial for achieving reliable circuit behavior.
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I'm trying to create a circuit that has 4 outputs, and loops over all of them so that only 1 output is high at each pulse.

Like this:
1 - 1
2 - 0
3 - 0
4 - 0

1 - 0
2 - 1
3 - 0
4 - 0

1 - 0
2 - 0
3 - 1
4 - 0

1 - 0
2 - 0
3 - 0
4 - 1

1 - 1
2 - 0
3 - 0
4 - 0

But, I'm getting race-condition errors inside my d-type flip-flop. So, I'm guessing it's something wrong with it.

Here is what it looks like:
http://folk.uio.no/thhildru/d-type.png

I don't really understand how a race-condition can happen here?
 
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Did you figure out the problem? Or do you still want help on this one?
 
Yup, I was trying to use a latch as a flip-flop. All worked out now :)
 
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