- #1
timeforplanb
- 16
- 0
Why do TTL integrated circuits assume unconnected inputs to be at logic level HIGH? Does the answer lie in the circuitry itself or some other factor?
TTL Gate Circuits: Unconnected Inputs Logic Level HIGH?
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Discussion Overview
The discussion centers on the behavior of TTL (Transistor-Transistor Logic) integrated circuits regarding unconnected inputs and their assumed logic level. Participants explore the underlying circuitry and logic implications, focusing on how unconnected inputs are treated as logic level HIGH and the effects on output states.
Discussion Character
- Technical explanation
- Conceptual clarification
- Debate/contested
Main Points Raised
- Some participants suggest that TTL circuits assume unconnected inputs to be HIGH due to the internal circuitry, where current flow determines the input state.
- One participant explains that if either input is grounded, the output transistor does not receive base current, resulting in a HIGH output.
- Another participant notes that for multiple input gates, it is logical to leave unconnected inputs HIGH, using a 4-input AND gate as an example.
- There is a request for clarification on the internal circuitry of TTL gates, including the roles of Vcc, inputs, and outputs, indicating uncertainty about the circuit diagram.
- A participant elaborates on the grounding effect, explaining how it affects the base current of the output transistor and the resulting output state.
Areas of Agreement / Disagreement
Participants express various viewpoints on the assumptions regarding unconnected inputs, with some agreeing on the logic behind treating them as HIGH, while others seek clarification on the circuitry involved. The discussion remains unresolved regarding the specifics of the internal workings of TTL gates.
Contextual Notes
Limitations include a lack of consensus on the detailed internal circuitry of TTL gates and the assumptions made about input states. Some participants express uncertainty about the roles of specific components in the circuit diagram.
- #2
vk6kro
Science Advisor
- 4,079
- 41
In the diagram, the inputs are only low if current flows out of the device at A or B. Otherwise, they are high.
If either of the inputs is grounded, then the output transistor will not get base current so the output will be high.
Only if both inputs are not grounded, ie high, then the output will be low.
This is a NAND gate, but the input logic is similar for other TTL devices
- #3
jedishrfu
Mentor
- 15,692
- 10,501
Not sure you'll get a definitive answer but it makes sense for multiple input gates to leave unconnected gates as high. As an example, a 4 input AND gate where you only need 3inputs you'd set the fourth one high.
Last edited:
- #4
timeforplanb
- 16
- 0
vk6kro said:
In the diagram, the inputs are only low if current flows out of the device at A or B. Otherwise, they are high.
If either of the inputs is grounded, then the output transistor will not get base current so the output will be high.
Only if both inputs are not grounded, ie high, then the output will be low.
I'm not that familiar with the internal circuitry of TTL gates yet. In the diagram, Vcc is one of the inputs right? Where is the other one? Do A and B represent the output terminals?
So, if the input is grounded we know that it goes through a certain circuit so we expect its output voltage to be low? Otherwise, it is high?
- #5
vk6kro
Science Advisor
- 4,079
- 41
timeforplanb said:
No, the inputs are A and B, but the output transistor gets its base current from Vcc via the base-collector diode of the odd-looking transistor at the left and the series resistor at left. The output is "Q".
Grounding either emitter robs the output transistor of its base current by providing a single diode path to ground for the base current of the output transistor, while the path through the output transistor's base involves two diodes and two diode drops.
So, all the base current goes via the left path.
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