I'm working on a design that requires me to control the output voltage on a line that will be used to drive a motor or other item. http://www.az-prod.com/vregcheck.jpg The above link goes to the schematic I have in mind. Please ignore the MOSFET symbols, I'm pretty sure I used a P-Channel mosfet on that schematic instead of an N-Channel mosfet, and I may have them wired wrong on the symbols, but they are correct when they convert to PCB (pin 1 is signal, pin 2 is ground, pin 3 is output for the mos's). Regardless, here's what I'm trying to do. An I/O chip will fire 1 of 4 I/O lines (designated I/O 1-4 on the schematic) which will in-turn connect the ADJ pin of the voltage regulator (LM317T, U1) to ground and to it's secondary resistor (R2-R5) to specify the voltage that will come out of the VREG. R1 is set to put out 100mA on the output line. The reason for the Mosfet's is because the specific type of I/O logic I'm using puts out a very small current, so the MOS's are bumping up the current to fire the VREG. All of this seems correct to me, however there is one question I can't quite answer. R6 is a pull-up resistor on the ADJ line of the VREG. What I'm trying to do here, is that when none of the I/O lines are firing, the ADJ pin is pulled high by R6, thereby turning off the VREG. When an I/O line fires, R6 is ignored and the VREG turns on (since it will then have a valid GND line through the MOS). Does this design work?