Why are PCB Trace and Layer Spacings Based on Voltage?

[js2020]

TL;DR Summary

Why is PCB space tracing based on voltage and not e-field intensity? Wouldn't the required spacing change with dielectric?

I understand that PCB trace spacing is typically based on a minimum found in certain standards and that is voltage based. If the breakdown strength of the dielectric is based on e-field intensity, wouldn't it be beneficial to actually consider the material properties and make it based on a maximum e-field intensity even if we consider some intensification factor due to the copper edge?

I have the same question about the layer spacing, even if we included some derating factor based on dielectric thickness.

 

[hutchphd]

Because the worst possible E field intensity is roughly max voltage over minimum spacing?.

 

[js2020]

Because the worst possible E field intensity is roughly max voltage over minimum spacing?.

That's not true. If you're talking about the "parallel plane" region directly between the conductors in a vertical stack then yes. If you're lookin at the conductor edges then no. The conductor edge can intensify the field quite a bit and this is the point where you will have most of your insulation degradation (due to e-field). Also, the breakdown strength of the dielectric is different whether you're measuring in the vertical or horizontal direction.

The assumption that you made is used for general board design but it is not necessarily true and is part of why you have to derate the dielectric as much as you do. So I was wondering why these factors are not considered more when designing boards, or maybe even if they are and there's a guide for it. Maybe the guide is the various standards but that wouldn't allow for material variations.

 

[hutchphd]

Two comments:

1. In my experience the worst problems with circuit boards in the real world always involve a combination of environment and spacing (like dendritic growth for instance). This is very difficult to model
2. Any real world analysis of anything will involve assumptions that are not necessarily true. The issue is the benefit of a slightly more compact board vs. the cost of the design analysis. Common practice evolves on this basis.

 

[js2020]

I can understand the environmental factors but even dendric growth seems to be e-field related. I guess point two really answers it though. The cost of the design analysis isn't worth it if the improvement in other metrics don't justify it.

 

[js2020]

So here's a question for best practices...what are the best practices to determine the net-to-net spacing and layer thickness on a layer within a multilayer PCB? Let's say L3 on a 4 layer PCB. I'm looking at a site (see link below) that gives 4 mm for an internal trace with 2 kV differential. Surely you wouldn't make your PCB 4 mm thick just to hold off 2 kV between inner layers with the traces stacked on top of each other.

https://www.smps.us/pcbtracespacing.html

 

[berkeman]

That's not true. If you're talking about the "parallel plane" region directly between the conductors in a vertical stack then yes. If you're lookin at the conductor edges then no. The conductor edge can intensify the field quite a bit and this is the point where you will have most of your insulation degradation (due to e-field).

And your extensive PCB layout experience tells you this?

Also, the breakdown strength of the dielectric is different whether you're measuring in the vertical or horizontal direction.

What?

 

[js2020]

And your extensive PCB layout experience tells you this?
What?

No, layout experience does not tell me that. E-field analysis will show that the field is intensified at the corners. I'm not sure what your question is? Do you not think it is?

What?

What I am saying is this. Let's say we test a laminate sample. The dielectric strength is higher measuring vertically through the laminate placing the electrodes on the "top" and "bottom" compared to placing the electrodes on each "side".

These two comparisons are similar to having two traces one above the other or having two planes/traces next to each other on the same layer.

Do you not think this is true? Please let me know if you disagree.

 

[Baluncore]

Breakdown voltage between layers, between tracks in the same layer, and between tracks on an external layer, are all different.

If you must use a PCB to support several small high voltage components, then use a single sided PCB. To reduce surface leakage mill slots through the PCB to lengthen the breakdown path.

Simply put, you should not be using multilayer PCBs for 2 kV supplies.

 

[Averagesupernova]

Breakdown voltage between layers, between tracks in the same layer, and between tracks on an external layer, are all different.

If you must use a PCB to support several small high voltage components, then use a single sided PCB. To reduce surface leakage mill slots through the PCB to lengthen the breakdown path.

Simply put, you should not be using multilayer PCBs for 2 kV supplies.

I would agree with everything said here. It seems the OP is trying to split hairs in a PC board layout concerning high voltages. There is really no place it is wise to 'split hairs' concerning high voltage. Plenty of room should be allowed for a margin of safety.
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Somewhat unrelated, but I'll tell a story of my days troubleshooting digital voltmeters. Had a production run of DVMs that were nothing too special. Successive approximation D/A converter, nothing spectacular for input resistance, something like 1Megohm. Measured up to 2000 volts AC or DC. The multiplier chain consisted of several resistors that totaled up to be the input resistance. One of these resistors was actually two in series placed in the circuit board that was laid out for only one resistor. The pair of resistors had one lead from each twisted together and soldered and the pair was then inserted into the board as one. I asked the engineer why this instead of one resistor. The reply was that it didn't work with just one of the correct value. When the voltage got high enough the DVM would give an inaccurate reading. He claimed to not know why. My take on it was a poor choice in resistors. The resistor got leaky when the voltage got high enough. Was not being run out of spec concerning watts, but likely voltage. A clear case of cutting it too close with high voltage. It's not intuitive that a resistor can get leaky without having arcs and sparks, but I am pretty sure this is what was happening. If the board was ever redesigned for use with two resistors actually inserted properly I don't recall.
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Edit: It's so long ago imy memory gets foggy. It might have only measured up to 1000 volts. In either case, the lesson is leave some room.

 

[js2020]

I don't think I'm splitting hairs. I'll find the references discussing the breakdown strength based on vertical electrodes, assuming the stackup is layers from top to bottom. The glass weave is not the same when looking vertically or horizontally. That's not considering the bonding with the prepreg which is likely a different glass style.

Even if we forget this and consider the dielectric isotropic, the copper itself creates field enhancements at the copper edges. I've posted a screenshot from a quick simulation I put together to show what I'm talking about. The two outer planes are at the same voltage, 3 kV, so the fields around it are symmetric at the middle conductor edge. The middle conductor is at 0V. I know, simulations do not contain all aspects of the physical component, but even in this simplified model it is clear that the e-field is intensified by almost three times compared to the parallel plane region. This is not considering the crescent profile the edge of the conductors will have after etching, but it is good for a simple illustration. Even if you triple your dielectric thickness, you may be operating your board closer to the breakdown strength than you think which is one of the key factors for aging, from my understanding at least. I appreciate the feedback if this is not correct. I posted this for discussion to see there was something I was missing with my understanding other than just being conservative and playing it save.

I think that PCBs can be operated at several kV with careful design.

 

[js2020]

 

[Baluncore]

I think that PCBs can be operated at several kV with careful design.

Careful design is required, but it must be done by an engineer with experience in diagnosing and repairing high voltage equipment. Given time, the common modes of equipment failure all show up in an electronics laboratory repair stream. There are so many possibilities that a neophyte, without several years of experience, can have no idea of what is really important. With experience, the competence of the designer is quickly revealed by the style of their PCB layout.

 

[DaveE]

Summary:: Why is PCB space tracing based on voltage and not e-field intensity? Wouldn't the required spacing change with dielectric?

I understand that PCB trace spacing is typically based on a minimum found in certain standards and that is voltage based. If the breakdown strength of the dielectric is based on e-field intensity, wouldn't it be beneficial to actually consider the material properties and make it based on a maximum e-field intensity even if we consider some intensification factor due to the copper edge?

I have the same question about the layer spacing, even if we included some derating factor based on dielectric thickness.

Because PCB layout standards are intended to be a useful and conservative guide to make reliable PCBAs in practice. It is easier for EEs to identify the voltages in a circuit and apply simple rules to create reliable products than to approach every trace on every PBC as a new and different electrostatics problem. In the real world we would rarely have the extra time or money to optimize every aspect of our designs. There is an art in real engineering in relying on the work others have done so you can avoid the calculations, testing, materials and vendor selection that new design rules might entail.

You may choose to argue about the details of why the standards are too conservative. However, if you worked for me and your circuit wasn't reliable because you thought you knew better, it would be the only time you would make that error.

 

[js2020]

You may choose to argue about the details of why the standards are too conservative. However, if you worked for me and your circuit wasn't reliable because you thought you knew better, it would be the only time you would make that error.

My goal with this post was not to argue. It was simply to get different perspectives on how to approach this to help with research ideas. I understand that everyone's answer has been to "be conservative" and doing do several kV on a PCB. Fortunately, I am doing this as research so I can afford to make mistakes and hopefully find interesting aspects that may not be investigated well.

I've already acknowledged earlier that I realize this approach may not be practical from the time perspective for engineers who are getting paid for every hour, unlike myself. The goal is to redesign components that can provide spacing, weight, and cost savings in each area by ~70% while also improving electrical performance. Who knows, maybe one day someone will be able to rely on the work I have done to avoid the calculations, testing, and material selection that a design from scratch would entail.

Thanks everyone who has provided some sort of feedback. Hearing reasons why people are so skeptical is also important. I see extensive testing in the future.

 

[DaveE]

My goal with this post was not to argue. It was simply to get different perspectives on how to approach this to help with research ideas. I understand that everyone's answer has been to "be conservative" and doing do several kV on a PCB. Fortunately, I am doing this as research so I can afford to make mistakes and hopefully find interesting aspects that may not be investigated well.

I've already acknowledged earlier that I realize this approach may not be practical from the time perspective for engineers who are getting paid for every hour, unlike myself. The goal is to redesign components that can provide spacing, weight, and cost savings in each area by ~70% while also improving electrical performance. Who knows, maybe one day someone will be able to rely on the work I have done to avoid the calculations, testing, and material selection that a design from scratch would entail.

Thanks everyone who has provided some sort of feedback. Hearing reasons why people are so skeptical is also important. I see extensive testing in the future.

The best research programs begin with a thorough literature search. You may be reinventing something that is common in all sorts of industries. There is/was HV circuitry in every CRT, X-ray machine, radar (ground, space and aircraft), microwave oven, and other applications too numerous to list. If you can reduce size, weight and cost each by 70% then you could make a lot of money.

 

[Rive]

...wouldn't it be beneficial to actually consider the material properties...

As far as I know if a new or special material is used then it's just like you said: instead of the standards used for regular PCBs the design is expected to be supported by a big load of calculations.

It's just those special carriers are not necessarily called 'Printed', and not always 'Boards'. PCBs are the cost effective stuff, either for design and for manufacturing. You should look for high voltage components and such instead.

Also, since an engineer usually expects some kind of uniformity to work with, the calculations and requirements are often provided by the manufacturer of the special technology.

 

[js2020]

The best research programs begin with a thorough literature search. You may be reinventing something that is common in all sorts of industries. There is/was HV circuitry in every CRT, X-ray machine, radar (ground, space and aircraft), microwave oven, and other applications too numerous to list. If you can reduce size, weight and cost each by 70% then you could make a lot of money.

Thanks for the suggestions. I am in no way trying to use this as my only source of information. I've reviewed literature in those areas which has helped me a lot. There is always more to read as you can find useful information in all areas.

Compared to the standard technology used for this application, it is a pretty large reduction as stated. I already have been working above 5 kV. I know I would need to do a full reliability analysis to say anything for sure, but I do check the partial discharge inception voltage (PDIV) and phase resolved PD pattern every so often looking for degradation. I just thought I would pick other brains on this and maybe have a meaningful discussion since everyone is so responsive on other questions. Again though, I am in now way trying to get all of my answers here.

 

[js2020]

As far as I know if a new or special material is used then it's just like you said: instead of the standards used for regular PCBs the design is expected to be supported by a big load of calculations.

It's just those special carriers are not necessarily called 'Printed', and not always 'Boards'. PCBs are the cost effective stuff, either for design and for manufacturing. You should look for high voltage components and such instead.

Also, since an engineer usually expects some kind of uniformity to work with, the calculations and requirements are often provided by the manufacturer of the special technology.

Hi Rive,
I think my post was poorly worded in terms of what I was asking and stating. I apologize for that because it has caused some confusion. Before I clarify, let me say that I understand the reason not to worry about this too much is because its easier to over design and not have to worry about it. The tried and true method works. I was hoping the discussion from this post would lean more towards discussion on failure mechanisms or maybe some physics behind it. But I 100% understand just being conservative so you know it will work.

This is research for me so I am ok with taking risks and failing. If anything, I figured this would be a good thread to discuss ideas and whatnot that maybe couldn't be investigated or tested because someone may work for a company that doesn't allow it or doesn't have the time/funds to support it. Or maybe even just someone has tons of knowledge in the area and wants to share.

This is moving on from the original questions and maybe someone would like to discuss.

I've posted some images of different glass styles...photos credit to Isola. When you tell the board house your board specifications, if you do not specify the glass style they will use whatever is most convenient for them. The weave is typically larger glass styles for thicker cores and prepreg for larger thicknesses and heaver copper, unless you specify. Good luck getting them to use exactly what you want in the first place, but when you do it may also drive up the cost. The thing is, understanding the way different glass types "behave" may allow the transition from those more traditional high voltage components you suggested to something cheaper. Solid dielectrics in HV offer excellent performance. The problem is the quality of the solids. Voids in the dielectric itself, or the bonding layer, can significantly reduce their rating. PCBs have a very good process which produces pieces with a low voids. That is one of the reasons transitioning to a PCB for some HV components is of interest.

Going to the picture linked...the black represents the resin epoxy. The white area is the glass strands. Datasheets you look at specify a dielectric strength, dielectric constant, etc for the specific thickness of dielectric tested, specific glass style, etc. Understanding how these properties effect the materials performance for stuff like signal processing is well known as impedance control is crucial. The properties of the glass styles are typically combined to get just the right properties for high speed PCBs. I bet these have a big impact on HV boards too

 

[Jody]

I'm confused.

Why or what does it mean that the electric field is "intensified" at the edges? What's that screenshot you're showing?

I've only worked a little a bit of high voltage and it was only a few hundred volts. I followed IPC standards it had guidelines for external and internal traces, and whether or not it was coated.

 

[js2020]

I'm confused.

Why or what does it mean that the electric field is "intensified" at the edges? What's that screenshot you're showing?

Sorry for the confusion. I've attached a new picture here with everything labeled. The voltages and spacing isn't necessarily important here as this is just to show a simplified example of what is really happening in the PCB in terms of e-field distribution.

This is an example of PCB cross section showing 3 internal layers. The two layers on the outside are at the same potential which is at 3 kV with respect to the inner layer. You can assume that the outer copper layers (3 kV) continue to the left, attaching to a via at some point. The middle layer (0 V) is pulled back due to clearance requirements from the 3 kV via. Finding the electric field with E=V/d assumes that you have parallel planes. That works great in the parallel plane region which is the area with uniform light blue as well as dark blue in the figure. However, when you look at the edge of the conductor, The e-field intensity goes from maybe ~5.5 kV/mm in parallel plane region to ~14 kV/mm. The only purpose of this was to illustrate that the e-field intensity at the conductor edges can be enhanced by a large factor.

As everyone above me has stated, considering the electric field in this way is not practical for every day designs, or "in real world" or "in real real engineering" as some here have put it.

 

[Jody]

Let's pretend you work for a really big company and they're willing to pay for you to consider the electric field of every design you're working you also have access to a high performance machine they got you the good stuff to speed things up... it's going to be for high volume production so it's worth the extra time to simulate and understand; make sure the risks have been minimized and maybe you're even pushing the design rules maybe the fabrication facility got back to with you feedback and they want to remove or change some parts of the design.

What's going on in your picture? It's just three metal layers the top and bottom are connected to a via and then I'm guess there's some port or VRM model connected between one of the outer metal layers to the internal one? Is there current? Which tool are you using or how do you get this plot?

I still admittedly don't feel like I understand what's going on in the picture or if it's normal although I don't normally work with high voltage.

 

[js2020]

What's going on your picture? It's just 3 metal layers the top and bottom are connected to a via and then I'm guess there's some port or VRM model connected between one of the outer metal layers to the internal one? Is there current? Which tool are you using or how do you get this plot?

I still admittedly don't feel like I understand what's going on in the picture or if it's normal although I don't normally work with high voltage.

I'm using Comsol Multiphysics here. Really, it can be done in any software that can solve electrostatics problems. That would include Matlab as well, as long as you define the system. Using something like Comsol, Ansys Maxwell, or the like simplify the problem since you can easily define shapes then set your boundary conditions. You literally build the picture to represent a cross sectional (or 3D) view of your system. To solve the problem you need to define the material properties for each shape (copper, PCB dielectric, air, etc). You also set your boundary conditions...In other words, define the potential of each conductor. So just know that the conductors have a potential on them. It doesn't matter where its coming from, you're just defining the potential. Since I'm interested in an electrostatics e-field, defining current through them is not necessary.

I've attached a few more images zoomed out more to show what's going on. This is the cross sectional view of a PCB near the via. Since the via is round, I'm only showing the left half of the cross sectional view. It has axial symmetry so if you rotate this about the y-axis you will get the same results. Only simulating one section saves time and reduces computational resources required. The white areas are conductors. They are white because the e-field was not calculated in this region. There is no need to calculate the e-field here because as a perfect conductor the e-field within is 0. You can ignore the red arrows. They're simply used to label where the e-field intensity is highest for each layer.

The e-field enhancement at the corner of a conductor is normal. If you were laying out a trace, you wouldn't want to make it shaped like a V because the e-field intensity would be really high at the corner. Instead, you would make it U-shaped to smooth out the fields. You can't do that for the edges of a conductor like this in a PCB since you're simply etching away a thin copper foil. That leaves you with an edge at the end of the conductor has a field enhancement as shown.

Hopefully that helps.

 

[pbuk]

The best research programs begin with a thorough literature search. You may be reinventing something that is common in all sorts of industries. There is/was HV circuitry in every CRT, X-ray machine, radar (ground, space and aircraft), microwave oven, and other applications too numerous to list. If you can reduce size, weight and cost each by 70% then you could make a lot of money.

I think it is safe to assume that the suppliers of { CRT, X-ray machine, radar (ground, space and aircraft) } have teams of engineers with decades of experience and extensive resources optimising every aspect of design. They are generally interesting people to share a beer with.

 

[js2020]

I think it is safe to assume that the suppliers of { CRT, X-ray machine, radar (ground, space and aircraft) } have teams of engineers with decades of experience and extensive resources optimising every aspect of design. They are generally interesting people to share a beer with.

It would be nice to meet a few! Hopefully PF has a few that come across this thread.

 

[Baluncore]

It would be nice to meet a few! Hopefully PF has a few that come across this thread.

They would walk away because you are insisting on using a PCB for multi-kilovolt supplies.
Dunning-Kruger applies; https://en.wikipedia.org/wiki/Dunning–Kruger_effect

Your feeling that PCB trace impedance is important in a power supply demonstrates you are following a fixative and ultimately irrational design path. A power supply is best analysed from the viewpoint of lumped impedance, not as signals on transmission lines. Folding HV circuits to loop out through one connector is more clever than it is intelligent.

The surface tracks on a PCB may work OK with high voltage for a year or more, until the material gets dust attracted to the surface. Then some seasonal condensation event initiates a surface breakdown and flash-over. Plasma and UV then burn the PCB dielectric, which does not take long, as every surface becomes blast-coated in a carbon and metal resistive film. The arc destroys the circuit integrity, then the fuse blows.

The edge of an internal layer of a PCB is not sharp for very long. Once you power the circuit, the dielectric decomposes until a radius is reached where it is sufficiently rounded to be stable in the short term. Then treeing progressively creeps through the dielectric volume, like pointed bamboo shoots through warm damp soil, searching out other conductors for the greatest potential difference. Why do you insist on creating internally vented trees that will mature in your absence ?
https://en.wikipedia.org/wiki/Electrical_treeing#Types_of_electrical_trees
https://en.wikipedia.org/wiki/Lichtenberg_figure

I have seen many X-ray power supplies that have failed through sheet circuit board material, even though the entire circuit was immersed in a tank of transformer oil to prevent surface arcing. The circuit board does not have tracks, it supports insulated standoffs with conductive spherical covers or rings bent over the junctions to prevent the oil being burnt.

You know there is a durability problem due to field intensity at the edges of PCB tracks. Maybe you have reached the point where you must learn from your own mistakes. Stop arguing as a form of procrastination, and do the job.
If you must use PCBs for surface mounted high voltage components, use a single layer board, with milled slots, and pot it all in epoxy so it might outlast a 3 year warranty.

 

[DaveE]

They would walk away because you are insisting on using a PCB for multi-kilovolt supplies.

Yes! This! For very HV work (> a few KV) you really want to avoid the interstitial boundaries between insulation materials. The trick is uniform, void free encapsulation.

 

[DaveE]

It would be nice to meet a few! Hopefully PF has a few that come across this thread.

I think you already have.