Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Why does lowering the slew rate lower the electrical noise?

  1. May 26, 2015 #1
    From my research I am showing that if an input signal becomes too slow (ie: a low slew rate) then the noise can cause multiple state changes.

    But I am being told that if the slew rate is low then it will get rid of unwanted noise.

    I read my results from this: (I lost the link but I did copy the text I was mostly interest in)
    upload_2015-5-26_14-35-7.png

    Am I just reading this out of context, or is what I've looked into correct for my assumptions?

    This is more of a request of interpretation of definitions rather than an application with numbers and formulas.
    I have read a couple of articles and the wikipedia description and I am afraid I have read conflicting things which may just be my fault.

    Thanks for the help,
    Dest
     
  2. jcsd
  3. May 26, 2015 #2

    berkeman

    User Avatar

    Staff: Mentor

    I know you didn't want a mathematical explanation, but if you are familiar with Fourier transforms, that is really the easiest way to explain it. Are you familiar with the differences between the Fourier transforms of a trapezoidal wave (slew-rate-limited square wave) and the transform of an ideal square wave? :smile:
     
  4. May 26, 2015 #3

    Merlin3189

    User Avatar
    Gold Member

    I do not read this in the text. I think you may be missing the context here,
    AFAIK the only way for low slew rates to reduce noise, is using slew rate to limit bandwidth. But then I would be worried that distortion would decrease the SNR.
    If you reduce noise while reducing SNR, you are worse off as a result.

    I shall be interested to hear the Fourier transform explanation for removing noise while maintaining SNR.
     
  5. May 26, 2015 #4
    These are two wildly different effects.

    At a high slew rate the circuit is being driven near it's upper frequency limit. There are a number of bad things that can happen at that point and which of them happen is somewhat random (ringing, capacitive feedback limiting gain, etc.). The solution is to either get a better device, or slow the slew rate down perhaps with a small filter (a cap).

    At a slow slew rate the problem is different. Suppose anything over 1V is considered a high and anything under 1V is considered a low. With a slow slew rate the voltage can pass through the 1V range so slowly that several "clock cycles" could pass. During this period the logic will not be able to decide if the level is a high or a low. So it will determine the logic level more or less randomly. Thus the output can swing back and forth randomly as well.

    There are logic devices that solve this problem by introducing some hysteresis. But apparently this device isn't one of them. If it's a problem, find a Shcmitt trigger buffer that has it.
     
  6. May 27, 2015 #5

    meBigGuy

    User Avatar
    Gold Member

    At low slew rates, the harmonic content of the signal is smaller, there is less crosstalk, less EMI generated, etc. So, low slew rates translate into less noise GENERATED by the signal itself. But, It also translates into problems when connected to a logic gate. Since the signal "hovers" near the switching point of the device for a longer period of time, the gate becomes susceptible to two effects. One is sensitivity to external noise superimposed on the signal (by whatever), and the other is shoot-through currents caused by pullup and pulldown devices within a logic gate both turning on at the same time (which causes noise that become imposed on the signal, etc etc).

    On the other hand, high slew rates contain more high frequency, require higher peak currents to create, etc (as the article you posted explained).

    So what is the optimum solution? There is always a tradeoff between the need for speed and the need for reliable transitions. If you force an IC to have faster transition times, it requires larger drivers, which means more capacitance, which means more power consumption. Also, you tend to get more glitches in complex logic, which also equates to more power.

    If you lower the transition requirement too far you get shoot-through currents, multiple transitions due to noise, etc. So both forces are at work. Actel is bragging about well they tolerate slow transition rates on its IO, probably by using schmitt-triggers (hysterisis).

    So, again, both forces are at work and the engineer must decide on the correct balance.
     
  7. May 27, 2015 #6
    @berkeman: As far as the (Graphical Convolution) responses for a trapezoidal wave and triangle wave (oops after I drew that I noticed you meant square wave, but I know that this is actually a triangle response of the same width time)
    upload_2015-5-27_9-41-21.png
    I am interested to here more explanation on this now assuming I have my trapezoidal wave convoluted right (it's been a while).

    I will need more time to look through everyone elses repsonse. Thanks for your time everyone!
    Dest
     
  8. May 27, 2015 #7

    berkeman

    User Avatar

    Staff: Mentor

    You have some good replies above to your two questions. My point about the difference in spectra between the square wave and a trapezoidal (repeating) waveform is that the energy in the harmonics is reduced for the slew-rate-limited trapezoidal waveform. That is the mathematical explanation behind why slew-rate limiting helps to "reduce noise" -- it is cutting down on the energy in the harmonics of the signal. :smile:
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook




Similar Discussions: Why does lowering the slew rate lower the electrical noise?
  1. Lowering impedance. (Replies: 17)

Loading...