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Homework Help: ADC and DAC

  1. Apr 30, 2015 #1
    1. The problem statement, all variables and given/known data
    I have always learnt (and read) that an increase in the number of bits causes the height of the 'step' on the graph to decrease. I tried to think about it but cannot come up with a proper explanation for this. THe books I read do not explain why?

    Can someone please explain in detail?

    2. Relevant equations
    No equation required, I think

    3. The attempt at a solution
    I think that more bits allow us to carry more information. But how does this decrease the height? Won't the difference in levels be the same. It's only more information can be carried. For example, the difference between level 10 and level 3 would still be the same no matter what the maximum level is, right?

    In all books, it says that increase the number of bits decreases the step height, but should it be increasing the sampling rate that does this.

    Anyway, how does increasing the sampling rate affect the signal then?
    Last edited: Apr 30, 2015
  2. jcsd
  3. Apr 30, 2015 #2


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    You have to think about the range. If you convert 0 to 10 V with a 10-bit device, you get 10 mV/bit. With a 20 bit device for the same range you get 10 ##\mu##V/bit

    The sampling rate tells you something about the highest frequencies you can digitize.
  4. Apr 30, 2015 #3

    rude man

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    An 8 bit adc with a max output of 10V has step size 10V/28. A 10-bit adc wit the same max output voltage has step size 10V/210.
  5. Apr 30, 2015 #4
    I have thought about this too.

    and let's take the case to be simple as you have said (even if the correct one is what rude man has said, I think).

    for a 10-bit,
    each 1V is represented by 1 level.

    for a 20-bit, each 1V is represented by 2 levels.

    Consider the difference between 3V and 5V. Would the 'step height' not be longer with the 20-bit??
  6. Apr 30, 2015 #5
    also, for the sampling rate.

    let's say at time = 1s, the voltage is 3V and at time 2s, the voltage is 5V

    If we increase the sample rate,
    at time =1s, voltage = 3V
    at time = 1.5s, voltage could be 4V.

    won't this decrease the step height?
  7. Apr 30, 2015 #6


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    I start to suspect you have a different picture of the working of this conversion. It is not so that 10 levels corresponds to 10 bits, not even for a flash adc (instead, the number of comparators needed for such an adc is indeed 2 to the power of (the number of bits - 1) ) . Read up a little on this process, eg in a good textbook, or google around a bit.
  8. Apr 30, 2015 #7
    could explain the quoted text in more details, and where i'm mistaking things, please
  9. Apr 30, 2015 #8


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    I wouldn't know where to begin. It would also take me an awful lot of time, most of it wasted on things you already know or aren't interested in. Better you read up first and then ask focused questions.

    Or I can start asking you questions and then play a teaching role. But that isn't really what this PF forums is all about. Let me try nevertheless:
    How do you think an adc works ? Describe in reasonable detail.

    That will also help in establishing at what level you actually need assistance, if any.
  10. Apr 30, 2015 #9
    Sorry, this would be too long for me too. Basically I know the basic, and I'm not interested in additional thing (how ads actually works, ...) that are not for the exam.

    what I want to know is why is it 'f you convert 0 to 10 V with a 10-bit device, you get 10 mV/bit.'? how did you get 10mV / bit?

    you don't need to start at the basics. I'l try to understand the quick explanation you would write.
  11. Apr 30, 2015 #10


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    Think of a simple sampling device: the input voltage is compared to the output of a device that adds ten voltages that are, respectively 5 V, 2.5 V, 1.25 V, 0.625 V, 0.3125 V, 0.156 V, 78 mV, 39 mV, 20 mV and (aha!) 10 mV. These voltages are offered under control of a counter that counts from 1 to 1024 and has a binary output. If the lsb (least significant bit) is 1, the 10 mV is ON, if it is 0 the 10 mV is OFF. The next bit controls the 20 mV, etc. The counter runs until the comparator says the voltage from the adder is greater than the input voltage.

    All this you could have read in the first [edit:] second link I gave you, so I really don't understand why you didn't look at it. Also I'm a bit flabbergasted at the ease with which you claim " Sorry, this would be too long for me too ". If that's really what you think, then stop wasting your time studying.

    [edit:] And I certainly won't go into explaining the frequency thing. The first link is excellent, so IF you want to know, read it.
    Last edited: Apr 30, 2015
  12. Apr 30, 2015 #11
    Sorry, don't take it badly.

    the level of physics required was that of A-level + it's just a very small part of the syllabus. Even now, these stuffs you just explained are still too complicated, as is the link you gave. At my level, I only need to be able to convert the 'curve' graph into a 'step' graph and say how it can be improved - that is, decrease height and increase sampling rate.
    Is it always 10 voltages always those you mentioned?
    is the smallest one always 10mV?

    may be an explain of how to arrive at this would be simpler.
    I think a line or 2 should suffice.
  13. Apr 30, 2015 #12


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    I'm trying not to take it badly (after all, you did get answers...); and your explanation clarifies things.

    Point is that for a binary number of N bits, there are ##2^N## possible values. Just like for a decimal number of M digits, there are ##10^M## possible values. Perhaps a picture (fig. 1 in link 2) for a three-bit digitization helps ?


    And if you add a fourth bit you have 16 steps. Same size step would mean double the range. Same range would mean double resolution (steps half as big).

    Reason I took 10 bits as an example is that it's so easy to remember that ##2^{10}=1024\approx 1000##. Reason Rudy took 8 bits is that 8 bits (one Byte) was the standard size of all things for a very long time.

    So: no, the numbers were just random examples. In practice there's all kinds of stuff to be had.

    Concerning the sampling rate: this applies to non-DC signals, the simplest being sine waves. If you don't take enough samples per second, you can't reconstruct the original signal from the digitized data. Figure 8 in link 1 shows an example of three sine waves that all give the same digitized result (the black dots):

    (or see figure 3 in same link)

    In my country we don't have A levels, so I still have no idea about level and/or age. But I grant you that link 1 was at a pretty high academic level. One of the most rewarding subjects I learned about at university.
  14. Apr 30, 2015 #13
    OK. but I still don't get one thing. With higher number of bits, more values (steps) would be obtained.
    But as for the 'height' of the step, how is it affect.

    let's say the range of voltage is 0 to 10.
    won't increasing the number of bits cause the height of the step between 2 specific voltages (say 3V and 5V) become even longer.

    By the way, It's cambridge A-level Physics, the applications part.

    I tihnk know how we reached the division at
    would really help.
    isn;t that divide telling us about the smallest voltage that can be converted. how is it about the height?
  15. May 1, 2015 #14
    can anyone clear this doubt this
  16. May 1, 2015 #15


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    Yes, you can: explain what it is that you don't understand. It is really really unclear to us what is blocking you.
  17. May 1, 2015 #16
    i understand the part that more information can be carried.

    but not why the step height decreases.

    let's say we have 128 levels (7-bit)

    for the voltages converted, we have 2V, 5V 10V, ...
    the 2V is on one level. will the 5V be on the next or will there be 3, 4 between them, even though they are not even in the original signal?

    if there is 3, 4, then i can't understand why the step height will decrease?
  18. May 1, 2015 #17


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    This part is completely unclear to me.

    As in post #2: You have to think about the range. The range (##E_{\rm FSR}## in the picture) and the number of steps are independent. The range is determined by a voltage divider or something (just like with an ordinary old-fashioned analog voltmeter) that reduces the desired range of voltages to be measured to the range of voltages the adc is designed for.

    The numbers 2, 5, 10 you mention look like ranges to me. Are you describing a particular instrument ?
    But then what's this about 3 and 4 and "the 2V is on one level, will the 5 be on the next" ?
  19. May 1, 2015 #18
    when converting analouge to digital, the binary codes are obtained. like 0010, 0110, ...

    from this, we can recover the analogue signal, which will now only be a steps.

    the voltages corresponds to the binary codes obtained from the original analogue signal.

    so, how does increasing the number of bits decrease the step height from the recovered analogue signal. won't the values of the voltages from the original analogue signal be the same, no matter what the number of bits is? if so, won't the difference between the voltages (in the recovered analogue signal, this is the step height) also remain the same?
  20. May 1, 2015 #19


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    Those are numbers. A voltage results by multiplying with a scale factor (in Volts). We are no no longer talking about an adc but about a dac.

    When digitizing, to e.g. 10 bits, the full scale of, say, 10 Volts is subdivided in 1024 steps of 10 mV (10 V/1024) each.
    When rendering the analog signal, every step in the digital signal is 10 mV, so 1111111111 is 10.24 V.
    0000000001 is 10 mV, 0000000010 is 20 mV. steps of 10 mV.

    When digitizing, to e.g. 12 bits, the full scale of, say, 10 Volts is subdivided in 4096 steps of 2.5 mV (10 V/4096) each.
    When rendering the analog signal, every step in the digital signal is 2.5 mV, so 111111111111 is 10.24 V.
    000000000001 is 2.5 mV, 000000000010 is 5 mV. steps of 2.5 mV.
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