BJT small signal analysis: output resistance

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Hello, I'm studying BJTs and I have a doubt about deriving the output resistance in the small signal equivalent circuit.

Let's consider the circuit below:
k1fnmt.png


To derive the output resistance, I'd write the following KCL:

[tex]i_x = i_{rc} + i_c[/tex]

at this point, every example I've seen says [tex]R_o = R_c[/tex], that is: the collector current is zero.

May someone please explain me the reason for this statement?

Thanks in advance.
 

Answers and Replies

  • #2
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It is my understanding if you want to find output impedance of the BJT, you don't have the Rc. Look at the collector curve in any transistor data sheet, they set up different Ib ( base current) and keep the base current constant. Then they vary the Vce and observe the change of the collector. Output resistance is:

[tex] \left |\frac {\partial I_c}{\partial V_{CE}}\right|_{ΔI_B=0}[/tex]

This is done by curve tracer.

Your drawing miss a few things, namely output resistance [itex]r_o[/itex]. And you don't want the 2.2K Rc there to drown out the [itex]r_o[/itex].
 
  • #3
uart
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Your drawing miss a few things, namely output resistance [itex]r_o[/itex]. And you don't want the 2.2K Rc there to drown out the [itex]r_o[/itex].
I'm pretty sure that his circuit is meant to be missing those things as it's a simplified analysis. It is common to ignore [itex]r_o[/itex] (or [itex]h_{oe}[/itex]) when the external Rc dominates it anyway. The output resistance that the student wants here is meant to include Rc. Of course it is actually just Rc, since [itex]r_o[/itex] is being ignored.
 
  • #4
uart
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[tex]i_x = i_{rc} + i_c[/tex]

at this point, every example I've seen says [tex]R_o = R_c[/tex], that is: the collector current is zero.

May someone please explain me the reason for this statement?
That's because with all the other sources set to zero, [itex]v_{be}[/itex] is zero, therefore [itex]v_{be}g_m[/itex] is zero.

To think of it another way, it is not possible for the voltage [itex]v_x[/itex] on the output side to cause any voltage on the input side (that is, at the base emitter junction). Be aware that this is a somewhat simplified model that you are dealing with.
 
  • #5
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I'm pretty sure that his circuit is meant to be missing those things as it's a simplified analysis. It is common to ignore [itex]r_o[/itex] (or [itex]h_{oe}[/itex]) when the external Rc dominates it anyway. The output resistance that the student wants here is meant to include Rc. Of course it is actually just Rc, since [itex]r_o[/itex] is being ignored.
Ha ha, just on the other post when I treat the question as simple transistor amp, turn out the OP did asked about early voltage and output resistance. I saw this post with the BJT model something like the Ebermal or something. I just look at it as real output resistance ro instead of just a simple circuit.

With the 2.2K, the output resistance is just 2.2K as ro is way into MΩ range.
 
  • #6
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eliotsbowe,

To derive the output resistance, I'd write the following KCL:

ix=irc+ic

at this point, every example I've seen says Ro=Rc, that is: the collector current is zero.

May someone please explain me the reason for this statement?
Why do you say the collector current becomes zero when Rc=Ro? Rc is part of Ro.

If you want to see the full equation for the output resistance, look at the attachment. As successive terms are set to zero or infinity, the equation simplifies. Finally, as ro becomes infinity, the output impedance becomes simply Rc.

Ratch
 

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  • #7
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Thanks everyone for the replies.
First of all, I have to apologize because my question wasn't exhaustive and I forgot to mention that the Early effect was being ignored in my example.
That said, uart's answer is what I was looking for:

That's because with all the other sources set to zero, [itex]v_{be}[/itex] is zero, therefore [itex]v_{be}g_m[/itex] is zero.

To think of it another way, it is not possible for the voltage [itex]v_x[/itex] on the output side to cause any voltage on the input side (that is, at the base emitter junction). Be aware that this is a somewhat simplified model that you are dealing with.
I just have one last doubt.
In order to assume [itex]v_{be}=0[/itex], a zero base current [itex]i_b[/itex] should flow through [itex]r_{\pi}[/itex], right? But once the [itex]i_x[/itex] current has flown through Rc, couldn't it reach the left side of the circuit and "turn on" currents [itex]i_b[/itex] and [itex]i_e[/itex]?
 
  • #8
uart
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I just have one last doubt.
In order to assume [itex]v_{be}=0[/itex], a zero base current [itex]i_b[/itex] should flow through [itex]r_{\pi}[/itex], right? But once the [itex]i_x[/itex] current has flown through Rc, couldn't it reach the left side of the circuit and "turn on" currents [itex]i_b[/itex] and [itex]i_e[/itex]?
Ok, say you apply KVL around the mesh on the left hand side (base emitter side) of your circuit. You should end up with something like:

[tex][ R_B + r_\pi + (1 + g_m r_\pi) R_E] i_b = 0[/tex]

Now since the part in the brackets is not zero, i_b therefore must be zero.

BTW. What I called R_B in the above equation is R_BB in parallel with R_in.
 
  • #9
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Ok, say you apply KVL around the mesh on the left hand side (base emitter side) of your circuit. You should end up with something like:

[tex][ R_B + r_\pi + (1 + g_m r_\pi) R_E] i_b = 0[/tex]

Now since the part in the brackets is not zero, i_b therefore must be zero.

BTW. What I called R_B in the above equation is R_BB in parallel with R_in.
That was helpful, thanks a lot!
 

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