Cascode Amplifier Small Signal Model

Join the discussion
Registration is free. Start your own thread to ask a follow-up.
13 replies · 7K views · last reply
CoolDude420
Messages
199
Reaction score
9

Homework Statement


Hi,

I'm just trying to derive the small-signal model of the cascode MOSFET amplifier circuit. In the lectures, we were just given the small-signal model directly. I'm trying to derive it.

I have almost the exact same thing except where I put the output voltage. In the lectures, it is put between D2 and S1,G2. However when I was deriving it, I put it between Ro2.

My derivation attempt:
Handwritten notes titled Cascode Amplifier showing a two-transistor circuit with M2 (common-gate stage, bias Vbias, output Vo, supply VDD and current source I) stacked over M1 (common-source stage, input Vi), followed by a small-signal model derivation of an NMOS MOSFET with gate-source voltage Vgs, transconductance gmVgs and output resistance ro.

Handwritten small-signal circuit for a cascode MOSFET stage: M1 with gate G1 at Vi=0 and source S1 grounded, stacked under M2 with gate G2 at Vbias=0 and drain D2 connected to Vo, with Vdd=0 and I=0 labeled at the top.

Handwritten small-signal model of a cascode MOSFET amplifier with MOSFETs replaced by SS model: two dependent current sources gm vgs in parallel with ro for each transistor, gates G1 and G2, sources S1 and S2, drains D1 and D2, input source vi and output vo across ro2.

Handwritten small-signal circuit redrawing of a cascode MOSFET amplifier: input source vi with vgs1 across G1 and S1,G2, a current source gm1 vgs1, transistor drain resistance ro1, a dependent source gm2 vgs2 with ro2 above, and output Vo marked across the right side.


Homework Equations

The Attempt at a Solution

 
Attachments
  • Handwritten notes titled Cascode Amplifier showing a two-transistor circuit with M2 (common-gate stage, bias Vbias, output Vo, supply VDD and current source I) stacked over M1 (common-source stage, input Vi), followed by a small-signal model derivation of an NMOS MOSFET with gate-source voltage Vgs, transconductance gmVgs and output resistance ro.
    1d7ebfcffd.png
    48.2 KB · Views: 1,950
  • Handwritten small-signal circuit for a cascode MOSFET stage: M1 with gate G1 at Vi=0 and source S1 grounded, stacked under M2 with gate G2 at Vbias=0 and drain D2 connected to Vo, with Vdd=0 and I=0 labeled at the top.
    449b8eaf00.png
    60.8 KB · Views: 1,325
  • Handwritten small-signal model of a cascode MOSFET amplifier with MOSFETs replaced by SS model: two dependent current sources gm vgs in parallel with ro for each transistor, gates G1 and G2, sources S1 and S2, drains D1 and D2, input source vi and output vo across ro2.
    4e8d28f0ba.png
    51.3 KB · Views: 1,401
  • Handwritten small-signal circuit redrawing of a cascode MOSFET amplifier: input source vi with vgs1 across G1 and S1,G2, a current source gm1 vgs1, transistor drain resistance ro1, a dependent source gm2 vgs2 with ro2 above, and output Vo marked across the right side.
    cff54f746a.png
    46.9 KB · Views: 1,402
  • Like
Likes   Reactions: berkeman
Physics news on Phys.org
scottdave said:
Isn't Vo supposed to be in reference to ground, not the other transistor?
Ah yes! Thank you.

One more question, how would I go about finding the voltage gain Vo/Vi? I have no idea where to start with it because Vo is at such an awkward position.(between D2 and gnd)

I'm assuming its a KVL loop involving ro1 ro2 and vo?
 
Last edited:
scottdave said:
2 loops should do it.

In the lecture notes we have,
it says that

$$V_{ro2} + V_o + V_{gs2} = 0$$
$$ V_{ro2} = (g_m)(v_{gs2})(r_{o2}) $$

How can you assume that all of the $$(g_m)(v_{gs2})$$ current flows through ro2??
 
CoolDude420 said:
How can you assume that all of the
(gm)(vgs2)​
(g_m)(v_{gs2}) current flows through ro2??

Where else is it going to go?
 
donpacino said:
Where else is it going to go?
through r01?
 
CoolDude420 said:
through r01?
how would it do that, current has to flow in a loop
 
donpacino said:
how would it do that, current has to flow in a loop
Ah yes. Just another question. If the gmvgs2 current only goes through ro2, and since there is no ground in that loop. Where does the current leave? I'm used to most circuits with a ground. I'm assuming it just disspitates through the resistor as heat?
 
CoolDude420 said:
If the gmvgs2 current only goes through ro2, and since there is no ground in that loop.

You don't need to have ground in a current loop.

your kvl, kcl, and ohms laws still apply here. The current doesn't need to "leave" it just needs to 'complete its loop'
 
I'm not where I can draw a picture, right now. In the loop which has r02: look at Node D2. The current entering and leaving that node must be equal, so the current through r02 must equal the source current.
 
donpacino said:
You don't need to have ground in a current loop.

your kvl, kcl, and ohms laws still apply here. The current doesn't need to "leave" it just needs to 'complete its loop'

Ah perfect. I get it now. Thank you!
 
scottdave said:
I'm not where I can draw a picture, right now. In the loop which has r02: look at Node D2. The current entering and leaving that node must be equal, so the current through r02 must equal the source current.

That makes perfect sense. Thank you.
 
scottdave said:
I'm not where I can draw a picture, right now. In the loop which has r02: look at Node D2. The current entering and leaving that node must be equal, so the current through r02 must equal the source current.

I just had a second thought. Doesn't that sort of disagree if we apply KCL at the other node(S2, D1)?

I apply KCL at the the middle node on the right side(S2, D1).
KCL at S2, D1 $$ g_mv_{gs,2} + i_{r_{o1}}= i_{r_{o2}} + g_mv_{gs,1}$$
Rearranging,
$$ g_mv_{gs,2} = i_{r_{o2}} + g_mv_{gs,1} - i_{r_{o1}}$$

That is telling me that in fact, not all of the current is going through r_o2.

What am I missing?