Design an Efficient System for Calculating Average of Recent Data Inputs

[perplexabot]

Hi all.

The question says:

Use the RTL design process to design a system that outputs the average of the most recent two data input samples. The system has an 8-bit unsigned data input I, and an 8-bit unsigned output avg. The data input is sampled when a single-bit input S changes from 0 to 1. Choose internal bitwidths that prevent overflow.

I have two questions. Firstly, is the data input sent following a clock cycle? If not, how do you know when a new datum is sent?

Secondly, how can you tell if the first two bytes are the same byte or different bytes but with equivalent values?

Thank you

 

[berkeman]

Hi all.

The question says:

Use the RTL design process to design a system that outputs the average of the most recent two data input samples. The system has an 8-bit unsigned data input I, and an 8-bit unsigned output avg. The data input is sampled when a single-bit input S changes from 0 to 1. Choose internal bitwidths that prevent overflow.

I have two questions. Firstly, is the data input sent following a clock cycle? If not, how do you know when a new datum is sent?

Secondly, how can you tell if the first two bytes are the same byte or different bytes but with equivalent values?

Thank you

It sounds like the data changes on the 1 --> 0 transition of the sample clock "S", and you should clock the data into your input register on the 0 --> 1 edge.

For each 0 --> 1 clock edge, you will clock in the new byte and clock the previous new byte into another register. Then what do you have to do with those two registers to take the average?

 

[perplexabot]

Oh I see. So the data input is implicitly half a cycle out phase with the register clocks (do I have the idea right?). I was actually thinking about using a clock divider, but I guess not any more.

And to answer your question, to take the average you would use an adder then a bit shifter (right shifter), am I right?

The computation is not my problem, it is how to store the first two bytes that is the problem for me. I'm going to give it another try with your comment in mind. Thanks for the reply.

 

[berkeman]

Oh I see. So the data input is implicitly half a cycle out phase with the register clocks (do I have the idea right?).

Yep. That's a pretty typical way that you manage your clocked systems.

And to answer your question, to take the average you would use an adder then a bit shifter (right shifter), am I right?

Yep again!

 

[perplexabot]

Wow, that's great. Another question if you don't mind me asking.

For each 0 --> 1 clock edge, you will clock in the new byte and clock the previous new byte into another register.

I am assuming you are implying to use two registers. But can this not be done with only one register (the other "register" would be the data from the data line)?

 

[berkeman]

Wow, that's great. Another question if you don't mind me asking.



I am assuming you are implying to use two registers. But can this not be done with only one register (the other "register" would be the data from the data line)?

The traditional synchronous way to do this would have 3 clocked 8-bit registers. The input register, the intermediate register, and the output register. What configuration are you thinking about exactly? And can you see some limitations with using less than 3 8-bit registers?

 

[perplexabot]

I was thinking (a rough algorithm):
clock the first data (rising edge) into input register
clock every other data (rising edge) into input register
when not clocking data into register on rising edge : use current data in dataline and register to compute.

I have not heard of the traditional method that you have mentioned, and no i can not see the limitations of using less than 3 registers.

PS: sorry for the misplaced thread

 

[berkeman]

I was thinking (a rough algorithm):
clock the first data (rising edge) into input register
clock every other data (rising edge) into input register
when not clocking data into register on rising edge : use current data in dataline and register to compute.

Well, if you had a lot more information about the timing of the input data stream, you might be able to make something work using both edges of the clock (if the data changed right after the 0 --> 1 clock edge, and was stable soon enough to meet the setup time requirements for the logic being clocked on the 1 --> 0 edge. But that's not usually how synchronous systems work. Generally only one clock edge is used as the "clock" to latch things into registers and flip-flops.

 

[perplexabot]

I am not using both edges. I am using only the rising edges.

 

[berkeman]

I am not using both edges. I am using only the rising edges.

But how are you going to "use current data in dataline" as part of the computation when it is changing between rising clock edges...?

 

[perplexabot]

Wow again, now I get what you meant by

Well, if you had a lot more information about the timing of the input data stream

. Ok so theoretically speaking, if the data in the dataline was stable at the moment when a computation called for it, then it would work. Is this correct? But, yes obviously this is very tedious, so I must change my approach.

 

[berkeman]

Wow again, now I get what you meant by . Ok so theoretically speaking, if the data in the dataline was stable at the moment when a computation called for it, then it would work. Is this correct? But, yes obviously this is very tedious, so I must change my approach.

Sounds like you get it. Good job!

 

[perplexabot]

Thank you for your time.

 

[perplexabot]

I have used 3 registers as you have mentioned. My output register contains the final computation (which I am using to send to a display). Should the period of the output register clock be twice as "S" since you need to go through two cycles of "S" to get a final output?

 

[berkeman]

I have used 3 registers as you have mentioned. My output register contains the final computation (which I am using to send to a display). Should the period of the output register clock be twice as "S" since you need to go through two cycles of "S" to get a final output?

It takes two clock cycles to load the queue. After that, each clock does what the problem statement asks for. You should probably state that in your homework submission.

For extra credit (at the PF if not in your class), how do the setup and hold time specs relate to the maximum clock frequency of your solution?

 

[berkeman]

Just out of curiosity, do students like you in the hyper-modern era cite Internet forum help threads as part of your online solutions?

EDIT -- Not being judgemental, just curious...

 

[perplexabot]

Sorry for the late reply, was taking a study break.

It takes two clock cycles to load the queue. After that, each clock does what the problem statement asks for. You should probably state that in your homework submission.

- I still don't understand how the final register's clock relates to S. I am NOT asking for answers, I am asking for help.

For extra credit (at the PF if not in your class), how do the setup and hold time specs relate to the maximum clock frequency of your solution?

- I don't understand your question (Oops! ). Specifically, what do you mean by "setup and hold time."

Just out of curiosity, do students like you in the hyper-modern era cite Internet forum help threads as part of your online solutions?

- I haven't thought of citing (and I haven't done so before). However, I would not mind doing so. As a matter of fact, I will do so for this homework (since you have helped extensively). I would like to let you know however, I highly doubt this homework is checked. Unfortunately we never get our homework back and I never know whether my design is correct. That is why I am here double checking if I am understanding the concepts. I have a bad professor (good person, bad teacher).

 

[berkeman]

All good responses.

Please google setup and hold times.

And please post a sketch of your solution so far. I think you are very close to the solution.

 

[perplexabot]

Here is my current work. Sorry about the bad quality but that is all I have. In the mean time I will google set up time and hold time. I think I have to get rid of the last register (output register). For the datapath image the boxes that are NOT the shifter and adder are registers.

 

[perplexabot]

After some reading and researching I think I got the answer to :

how do the setup and hold time specs relate to the maximum clock frequency of your solution?

The setup time should be enough for the byte to travel to the gates of the register (or the register to read the data) and the hold time should be enough for the data to be stable and pass through the register (or the register to act upon data).

I am embarrassed I did not know what hold time and setup time meant.