Determining transistor sizes equal to a single inverter

AI Thread Summary
To determine transistor sizes for a 2-input NAND gate equivalent to a single inverter with Wn = 1 µm and Wp = 2 µm, the worst-case pull-up and pull-down conditions must be considered. The equivalent W/L ratios for the NAND gate's pull-down network (PDN) and pull-up network (PUN) should match those of the inverter under worst-case timing scenarios. Initially, the attempt to equate the W/L ratios did not yield correct results due to overlooking the worst-case requirement. Upon reevaluation, it was clarified that the worst-case equivalent W/L for the NAND gate should align with the given Wp and Wn values. Understanding this concept is crucial for accurately sizing transistors in digital logic design.
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Homework Statement



Determine transistor sizes for (lets say a 2 input nand gate, my actual question is more complicated but i want to know the basic idea so i can do it myself) so that the worst case pull down and pull up is equivalent to a single inverter with Wn = 1 micro m and Wp= 2 Micro m
All transistor lengths are 0.25 micro meters


Homework Equations


Basic Mosfet knowledge should do i guess.


The Attempt at a Solution


i know the solutions, i just don't know how to arrive at it.
My guess was that the equivalent transistor W/L for the PDN or PUN should be the same as the W/L for the PDN or PUN of the inverter. But the numbers don't add up.
 
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Guys i think I've got it but I am not sure

the question said WORST CASE... i was basically missing that part.
so now that I've read it carefully I've found out (with working backwards on the solutions) that using the worst case scenario (slowest timing aka lowest equivalent W/L for PDN or PUN of the nand gate) your equivalent w/l of the worst case scenario should equal to the Wp or Wn given in the question.
 
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