- #1
JOZ
- 7
- 0
Hi I've got a problem with VHDL code its comming up with a lot of errors saing that there's undefined symbols, so I am pretty sure that the error is to do with defining things/instantiation, below is all the code for both the files that are being used
The other files is:
Code:
----------------------------------------------------------------------------------
-- Traffic.vhd
--
-- Traffic light system to control an intersection
--
-- Skeleton - Add your comments here!
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Traffic is
Port ( Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
-- for debug
debugLED : out std_logic;
-- Car and pedestrian buttons
CarEW : in STD_LOGIC; -- Car on EW road
CarNS : in STD_LOGIC; -- Car on NS road
PedEW : in STD_LOGIC; -- Pedestrian moving EW (crossing NS road)
PedNS : in STD_LOGIC; -- Pedestrian moving NS (crossing EW road)
-- Light control
LightsEW : out STD_LOGIC_VECTOR (1 downto 0); -- controls EW lights
LightsNS : out STD_LOGIC_VECTOR (1 downto 0) -- controls NS lights
);
end Traffic;
architecture Behavioral of Traffic is
-- Encoding for lights
constant RED : std_logic_vector(1 downto 0) := "00";
constant AMBER : std_logic_vector(1 downto 0) := "01";
constant GREEN : std_logic_vector(1 downto 0) := "10";
constant WALK : std_logic_vector(1 downto 0) := "11";Component Timer
Port ( clr : in STD_LOGIC;
clock : in STD_LOGIC;
globalReset : in STD_LOGIC;
load : in STD_LOGIC;
Sec5 : out STD_LOGIC;
Sec2 : out STD_LOGIC;
Sec1 : out STD_LOGIC);
end Component;
Begin
T1 : Timer PORT MAP (
clr => clr,
clock => clock,
globalReset => globalReset,
load => load,
Sec5 => Sec5,
Sec2 => Sec2,
Sec1 => sec1,
);
type StateType is (GreenRed, AmberRed, RedGreen, RedAmber, WalkRed, RedWalk, RedGed, GedRed);
signal state, nextstate : StateType;
HPedEW :STD_LOGIC; -- Hold value of PedEW
HPedNS :STD_LOGIC; -- Hold value of PedNS
debugLed <= reset; -- Show reset status on FPGA LED
LightsEW <= RED;
LightsNS <= GREEN;
----process which changes to the next state on the clock edge
ChangeState:
process(globalReset, Clock)
begin
if (globalReset = '1') then
state <= GreenRed;
elsif rising_edge(clock) then
if(HPedNS='0') then
HPedNS<=PedNS;
end if;
if(HPedEW='0') then
HPedEW<=PedEW;
end if;
state <= nextstate;
end if;
end process ChangeState;-----state machine which chooses what the next state will be
StateMachine:
Process(state, CarEW, CarNS, HPedEW, HPedNS, Sec1, Sec2, Sec5)
begin
-- default state is GreenRed
case state is
when GreenRed =>
LightsNS <= GREEN;
LightsEW <= RED;
if ((HPedEW = '1') or (CarEW = '1')) and (Sec5='1') then
resetCount;
nextstate <= AmberRed;
elsif (HPedNS = '1') and ((Sec2='0') or ((HPedEW = '0') and (CarEW = '0')) then
loadCount<=’1’;
nextstate <= WalkRed;
end if; when WalkRed =>
LightsNS <= WALK;
LightsEW <= RED;
loadCount<=’0’;
if(Sec5='1') then
resetCount;
nextstate <= GreenRed;
HPedNS<='0';
end if; when AmberRed =>
LightsNS <= AMBER;
LightsEW <= RED;
if(Sec1='1') then
resetCount;
nextsate<=RedGed
end if;
when RedGed =>
LightsNS <= RED;
LightsEW <= RED;
if(Sec1='1') then
resetCount;
if (HPedEW = '1') then
loadCount<=’1’;
nextstate <= RedWalk;
else
nextstate <= RedGreen;
end if;
end if;
when RedGreen =>
LightsNS <= RED;
LightsEW <= GREEN;
if ((HPedNS = '1') or (CarNS = '1')) and (Sec5='1') then
resetCount;
nextstate <= RedAmber;
elsif (HPedEW = '1') and ((Sec2='0') or ((HPedNS = '0') and (CarNS = '0')) then
loadCount<=’1’;
nextstate <= RedWalk;
end if; when RedWalk =>
LightsNS <= RED;
LightsEW <= WALK;
loadCount<=’0’;
if (Sec5='1') then
resetCount;
nextstate <= RedGreen;
HPedEW <='0';
end if;
when RedAmber =>
LightsNS <= RED;
LightsEW <= AMBER;
if(Sec1='1') then
resetCount;
nextstate<=GedRed
end if;
when GedRed =>
LightsNS <= RED;
LightsEW <= RED;
if(Sec1='1') then
resetCount;
if (HPedNS = '1') then
loadCount<=’1’;
nextstate <= WalkRed;
else
nextstate <= GreenRed;
end if;
end if; end case;
end process StateMachine;end;The other files is:
Code:
----------------------------------------------------------------------------------
-- timer module
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;entity Timer is
Port ( clr : in STD_LOGIC;
clock : in STD_LOGIC;
globalReset : in STD_LOGIC;
load : in STD_LOGIC;
Sec5 : out STD_LOGIC;
Sec2 : out STD_LOGIC;
Sec1 : out STD_LOGIC);
end Timer;
architecture Behavioral of Timer is
signal count : natural range 0 to 501;
beginprocess(globalReset, clock) is
begin
if globalReset = '1' then
count <= 0;
elsif (count <= 500) and (rising_edge(clock)) then
if clr = '1' then
count <= 0;
elsif load = '1' then
count <= 200;
load <= '0';
else
count <= count + 1;
end if;
end if; if count >= 100 then Sec1 <= '1';
else Sec1 <= '0';
end if;
if count >= 500 then Sec5 <= '1';
else Sec5 <= '0';
end if;
if count >= 200 then Sec2 <= '1';
else Sec2 <= '0';
end if;
end process;
end Behavioral;
