Engineering Flip Flops, and equivalent circuits

[sandy.bridge]

Homework Statement

Hey guys,
Can someone please explain how the following circuits that I attached are equivalent? I'm not seeing that they are when I develop equations for the output Z.

For the first one I get Z=Q1+Q2=(Q1'+Q2')+(XQ2')'=Q1'+Q2'+X'+Q2

For the second image I get Z=Q2'+Q1=(XQ2')'+Q1=X'+Q2+Q2+Q1'

so I must be messing up somewhere and not catching it.
Any suggestions?
Thanks!

 

[berkeman]

Homework Statement

Hey guys,
Can someone please explain how the following circuits that I attached are equivalent? I'm not seeing that they are when I develop equations for the output Z.

For the first one I get Z=Q1+Q2=(Q1'+Q2')+(XQ2')'=Q1'+Q2'+X'+Q2

For the second image I get Z=Q2'+Q1=(XQ2')'+Q1=X'+Q2+Q2+Q1'

so I must be messing up somewhere and not catching it.
Any suggestions?
Thanks!

The AND/NAND and the 2nd flop do not look right...

 

[sandy.bridge]

Are you referring to the image or the equations that I have given? If it's the equations, the first one?

 

[berkeman]

The image -- the connections do not look equivalent (but I could be wrong).

 

[berkeman]

Where did you get the image from?

 

[sandy.bridge]

Second image I copied directly out of the textbook. The first image is the solution. It is asked for one to determine an equivalent circuit using merely NAND and NOR gates, and no inverters. The top image is answer.

 

[sandy.bridge]

Would you agree that the equations I presented to represent the figures are indeed correct? Perhaps the solution is wrong?

 

[berkeman]

Second image I copied directly out of the textbook. The first image is the solution. It is asked for one to determine an equivalent circuit using merely NAND and NOR gates, and no inverters. The top image is answer.

Would you agree that the equations I presented to represent the figures are indeed correct? Perhaps the solution is wrong?

I get the same two Z equations as you do.

However, when I start to fill out a State Table for the two circuits, they behave differently. Start with the FFs cleared and X=0 at the input. The initial state has different Z values. As you clock the two circuits while holding X=0, they stabilize into two different state looping behaviors, but each of those has Z=1 at the output. When I change the input to X=1, I get a different value of Z output for the two circuits, depending on what part of the two looping state behaviors the circuits are in when the input X is changed. That doesn't seem like functionally equivalent circuits to me...

Try it yourself. Set up the two state tables and fill in some values for each clocked cycle:

For circuit #1:

STATE  X  Q1  Q1'  Q2  Q2'  --> Z
    0     0   0    1     0    1         0
    1     0   1    0     1    0         1
and so on...

For circuit #2:

STATE  X  Q1  Q1'  Q2  Q2'  --> Z
    0     0   0    1     0    1         1
    1     0   1    0     0    1         1
and so on...

I may have made some errors in my State Tables, so I'd be interested in what you find. It looks like the two circuits have different State Diagrams at least, and for me it looks like they give different outputs for at least one sequence of inputs X.

 

[sandy.bridge]

I did, and I could not seem to get that they were equivalent. Hmm. Is there a strategic way to determine an equivalent circuit to the second image (green and red) using merely NAND and NOR gates? I feel as though I have been staring at this problem for LONG.