Engineering Having Trouble Solving Circuits Questions? Get Help Here!

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The discussion revolves around two circuit questions involving waveform analysis. The first question requires plotting output waveforms for a pulsed aperiodic wave, while the second involves determining the output waveform for a uniform square pulsed wave. The user is struggling with conceptual errors in both questions and seeks guidance on methodologies rather than direct solutions. Clarifications on feedback mechanisms and assumptions about initial states are also discussed, particularly in relation to NOT gate behavior. The conversation emphasizes the importance of understanding time constants and circuit behavior to derive the correct waveforms.
therash09
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I am having problems in solving two questions belonging to Circuits.

Question 1 can be found at the link given below:
https://picasaweb.google.com/116360607158194937783/RandomPictures#slideshow/5765362642755310706
Given is a circuit having a pulsed aperiodic wave pattern, Vi. To be plotted are output waveform Vo, waveform across capacitor Vc and waveform across resistor Vr.

Question 2 can be found at the link given below:
https://picasaweb.google.com/116360607158194937783/RandomPictures#slideshow/5765362645530396946
To be found is the output waveform Vo, if the input to the circuit is a uniform square pulsed wave pattern.

While I have been able to almost entirely do Question 2, there seems some very basic conceptual error not leading to the correct answer. As for Question 1, I could find very little headway.

It would certainly not be possible for anyone to plot the waveforms here, and I do not expect anyone to plot the same for me on any other platform. What I require is the method to proceed with these questions and the steps, particularly for Question 1. The required waveforms could be vaguely mentioned in statements, as these answers shall be of utmost help, alongside the methodologies!

I will be extremely thankful to everyone who answers!EDIT: Thanks a lot Jony130! The links are working now. :)
 
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But the link you post don't work. So we can not see any imagine.
 
As for the Q1 simply assume that the time constants T= R*C is equal 1T and the gate switch when the voltage reach 0.5Vdd
Or look on the web Gate Monostable circuit.
http://www.electronics-tutorials.ws/waveforms/monostable.html
http://forum.allaboutcircuits.com/showthread.php?p=486213#post486213
 


Thanks Jony130!

Perhaps, I've got you. You mean the input to the NOT Gate is a trigger- and outcome of RC-circuit, considering the time constant is very small. But given the feedback, I am finding it tough to solve. Should I assume some initial state and proceed? How will the output waveform differentiate for each high pulse? The trigger will possibly be the same, except that the two corresponding NOT outputs would be separated gradually. Is that right? And regarding the voltage across capacitor, could you help me out?

Kindly elaborate in few words. Feedback questions seem a bit tougher to solve. :)

In Q2, should the output be interleaved high level triggers (low level triggers blocked by diode) as in Half Wave Rectifier, or all high level triggers- I mean the low level triggers are inverted and the output is all high level triggers without missing any trigger stage, as in Full Wave Rectifier, considering the input is between some +ve and -ve voltage levels? Kindly help!
 


therash09 said:
Perhaps, I've got you. You mean the input to the NOT Gate is a trigger- and outcome of RC-circuit, considering the time constant is very small. But given the feedback, I am finding it tough to solve. Should I assume some initial state and proceed?
Yes. that's how you solve these arrangements. You can assume any initial state you like, :smile: but you'll generally find only one will be consistent through the whole circuit and/or do anything useful.

For example, consider that NAND gate. You can, to start with, assume the feedback line is a LO, or you can assume it's a HI.

- if it's a LO, explain what happens at the NAND gate's output when Input Vi transitions from LO to HI.

- if it's a HI, explain what happens at that gate's output when Input Vi transitions from LO to HI.

What conclusion can you draw?
In Q2, should the output be interleaved high level triggers (low level triggers blocked by diode) as in Half Wave Rectifier, or all high level triggers- I mean the low level triggers are inverted and the output is all high level triggers without missing any trigger stage, as in Full Wave Rectifier, considering the input is between some +ve and -ve voltage levels? Kindly help!
[/color]For this circuit, let's assume that the diode is not present. Sketch the waveform you'd expect to see across the resistor. Make whatever assumption you like about the time-constant τ[/size]= ℝ.ℂ
 
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