If both inputs in SR latch are zero

If both the inputs in SR latch are zero and there was no previous output then what would be the output? If both the NOR gates are different then depending which one is faster the output will be accordingly, but what if both are identical?

If both the NOR gates are different then depending which one is faster the output will be accordingly, but what if both are identical?

They can't be identical. One will always have slightly higher gain or speed. It also may by that the designers deliberately bias the SR Latch to favor one output.

They can't be identical.
Why cannot they be identical ? Of course it would be very rare but still if they are then what?

Averagesupernova
Gold Member
I suspect you don't understand how the outputs are configured and wired together. If you did you would know the answer.

I suspect you don't understand how the outputs are configured and wired together. If you did you would know the answer.
I think I know how they are configured and wired but maybe I have some misunderstanding. Help me understand it. I don't get why they can't be identical

NascentOxygen
Staff Emeritus
Why cannot they be identical ? Of course it would be very rare but still if they are then what?
Even if all else is identical, random electrical noise will tip one output faster towards one state or the other, and this in turn forces the other output towards the complementary state.

Averagesupernova
Gold Member
Voltage going positive on Q reinforces the voltage going negative on /Q. They reinforce each other to go opposite directions. Without a schematic that is the best I can explain it.

Okay I just figured out that I don't understand the basic SR latch properly. I am continuously finding myself in the chicken-or-egg first position.
Let's say S input is 1 and R input is 0. So for the first NOR gate to give input it has to get the output from the other NOR gate but it won't get it until it give its own output!
Maybe because I have not studied how a gate works internally I am having trouble but still if anyone can help me understand, it would be great.
Thank You

This is a known problem with the ideal SR latch with perfectly matched gates. If the gates have any mismatch in delay, like a real latch will, then the circuit will find a stable state. The only problem is, you don't necessarily know which gate is slower.

So like the old joke goes, if it hurts, then don't do that.

http://www.cs.ucr.edu/~ehwang/courses/cs120b/flipflops.pdf

"A problem exists if both S' and R' are de-asserted at exactly the same time as shown at time t6. If both gates have exactly the same delay then they will both output a 0 at exactly the same time. Feeding the zeros back to the gate input will produce a 1, again at exactly the same time, which again will produce a 0, and so on and on. This oscillating behavior, called the critical race, will continue forever. If the two gates do not have exactly the same delay then the situation is similar to de-asserting one input before the other, and so the latch will go into one state or the other. However, since we do not know which is the faster gate, therefore, we do not know which state the latch will go into. Thus, the latch’s next state is undefined.
In order to avoid this indeterministic behavior, we must make sure that the two inputs are never de-asserted at the same time. Note that both of them can be de-asserted, but just not at the same time. In practice, this is guaranteed by not having both of them asserted. Another reason why we do not want both inputs to be asserted is that when they are both asserted, Q is equal to Q', but we usually want Q to be the inverse of Q'."

They can't be identical. One will always have slightly higher gain or speed. It also may by that the designers deliberately bias the SR Latch to favor one output.

Does this work? If phase of the S and R falling edge equals the mismatch then you're back into the same situation, no? It seems like the external rule imposed on the driving circuit of "don't let S and R falling edges be within the time of the worst case possible mismatch" is the only thing that works for the basic cross coupled latch.

Does this work? If phase of the S and R falling edge equals the mismatch then you're back into the same situation, no? It seems like the external rule imposed on the driving circuit of "don't let S and R falling edges be within the time of the worst case possible mismatch" is the only thing that works for the basic cross coupled latch.

Nevermind, I just realized it would get cleaned up on the next cycle around. So it is different in the sense that the oscillation doesn't persist.

vk6kro
Okay I just figured out that I don't understand the basic SR latch properly. I am continuously finding myself in the chicken-or-egg first position.
Let's say S input is 1 and R input is 0. So for the first NOR gate to give input it has to get the output from the other NOR gate but it won't get it until it give its own output!
Maybe because I have not studied how a gate works internally I am having trouble but still if anyone can help me understand, it would be great.
Thank You

No, there is no chicken-egg situation with a SR flipflop.

Have a look at this circuit which is from Wikipedia:
http://dl.dropbox.com/u/4222062/SR%20FFlop.PNG [Broken]

It is made of 2 NOR gates. A NOR gate output is high unless one (or both) of the inputs is high. Then it goes low.

So, in the diagram the R input is high (shown as red in the diagram), so the output of that gate has to be low because it is a NOR gate.

The S input is low and the output from the top gate is low, so the lower gate has to have a high output.

This means that the top gate has to have a low output even if the R input is removed, because one of its inputs is still high.

Every time you make an input high, the input next to it on the same gate goes high and stays high.

You can see from this diagram, that if both inputs were high, then both outputs would be low. This is because each NOR gate has a high input and so its output must be low. This is not a problem.

The problem with this circuit is that if the gates were identical, there could be oscillation when you first turned it on. Both inputs would be low but both outputs would become high at the same time, forcing the outputs to go low. Very unfortunate oscillation would possibly happen until an input pulse hopefully forced the oscillation to stop.

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NascentOxygen
Staff Emeritus
I'm not sure that the whole story has been told here. Logic gates come in two basic versions: buffered and unbuffered. Let me demonstrate the distinction. A buffered inverting gate cannot have its output connected back to its own inputs without causing logic oscillations, as an example, a NOR gate with both inputs connected together. On the other hand, an unbuffered inverting gate cannot have its output connected back to its inputs and still produce a logic output. (It instead acts as a linear amplifier, with output settling around 2-3 volts for TTL, and can in fact be used as a rudimentary amplifier, e.g., to amplify audio tones.)

If an SR latch is constructed using a pair of buffered gates, then in the worst case scenario it could exhibit continuous logic level oscillations as mentioned. But if constructed using two unbuffered gates, I think we'll see the electronics race to immediately attain a stable state with no logical oscillations.

I think it's called "invalid state", you may try to add some control logic gates to enable and disable the SR latch

vk6kro