I simulate the NMOS in LT Spice. And for vGS=0, I observe that the leakage current starts at a certain value then decreases suddenly and then slightly increases with vDS. For vGS different than 0 (positive or negative) but smaller than the threshold voltage, I observe that the leakage current starts at 0, then increases slightly with vDS. What is happening? In my textbook it does not tell about this. It only tells that iDS = 0. I know they only approximate but where should I look for more information? What is the theory?