Investigating NMOS Leakage Current with LT Spice

In summary, the conversation discusses the observation of leakage current in an NMOS simulation, with varying values of vGS and vDS. For vGS=0, the leakage current starts at a certain value and then decreases suddenly, before slightly increasing with vDS. For vGS different than 0 but smaller than the threshold voltage, the leakage current starts at 0 and then increases slightly with vDS. The individual is wondering about the theory behind this behavior and where to find more information. They also mention observing a similar trend when starting with a high vDS and sweeping down to 0. There is a question about the accuracy of the model in the subthreshold region, which the individual cannot provide help with. A related resource is mentioned
  • #1
RaduAndrei
114
1
I simulate the NMOS in LT Spice.
And for vGS=0, I observe that the leakage current starts at a certain value then decreases suddenly and then slightly increases with vDS.
For vGS different than 0 (positive or negative) but smaller than the threshold voltage, I observe that the leakage current starts at 0, then increases slightly with vDS.

What is happening? In my textbook it does not tell about this. It only tells that iDS = 0. I know they only approximate but where should I look for more information? What is the theory?
 
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  • #2
What happens if you start with high Vds and then sweep down to 0? I'm wondering whether the bias solution is at issue when Vgs and Vds are both zero.
 
  • #3
If I sweep Vds from 20V to 0V with vGS = 0, then iDS starts at 60pA, then it falls very slowly, then at vDS = 1V or so, it quickly rises to 400pA. (see picture)
If vGS is not 0 but lower than Vt, then iDS starts at 54 pA, then it falls until vDS = 1 with some slope, then after vDS = 1, it quickly falls to 0 pA or so.

If vGS is greater than Vt, then iDS starts at the saturation current, then it stays constant, then it falls to 0. This part I understand.

I would say that I also understand the part where vGS is not 0 but lower than Vt. For a given vGS, the leakage current increases with increasing vDS. It's common sense.
But for vGS = 0, I do not understand what is happening or where to look.
 

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  • #5
Ok, thanks.
 

1. What is NMOS leakage current?

NMOS leakage current refers to the current that flows through the drain-source channel of an NMOS transistor when the transistor is supposed to be in the off state. This leakage current can occur due to various factors such as subthreshold conduction, gate oxide leakage, and junction leakage.

2. Why is it important to investigate NMOS leakage current?

Investigating NMOS leakage current is important because it can significantly affect the performance and reliability of electronic devices that use NMOS transistors. Excessive leakage current can result in power consumption, reduced battery life, and even failure of the device. By understanding and analyzing the factors contributing to NMOS leakage current, scientists can develop strategies to minimize its impact and improve device efficiency.

3. How is LT Spice used to investigate NMOS leakage current?

LT Spice is a computer program that simulates the behavior of electronic circuits. It can be used to create a circuit model of an NMOS transistor and analyze its leakage current under different operating conditions. By changing input parameters such as gate voltage and temperature, scientists can observe the effect on the leakage current and gain insight into the underlying mechanisms.

4. What are some common techniques for reducing NMOS leakage current?

There are several techniques that can be used to reduce NMOS leakage current, including optimizing device design and fabrication processes, using specialized materials for the transistor channel, and implementing circuit-specific biasing techniques. Additionally, advanced simulation tools like LT Spice can be used to identify and address specific sources of leakage current in a circuit.

5. Can LT Spice accurately predict NMOS leakage current in real-world scenarios?

While LT Spice is a powerful tool for simulating electronic circuits, its accuracy is limited by the accuracy of the device models and input parameters used. Therefore, it is essential to validate the simulation results with real-world measurements. Additionally, other factors such as device aging and variability in manufacturing can also affect NMOS leakage current in real-world scenarios.

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