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NMOS Transistor

  1. Nov 30, 2015 #1
    I simulate the NMOS in LT Spice.
    And for vGS=0, I observe that the leakage current starts at a certain value then decreases suddenly and then slightly increases with vDS.
    For vGS different than 0 (positive or negative) but smaller than the threshold voltage, I observe that the leakage current starts at 0, then increases slightly with vDS.

    What is happening? In my textbook it does not tell about this. It only tells that iDS = 0. I know they only approximate but where should I look for more information? What is the theory?
  2. jcsd
  3. Nov 30, 2015 #2


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    What happens if you start with high Vds and then sweep down to 0? I'm wondering whether the bias solution is at issue when Vgs and Vds are both zero.
  4. Dec 1, 2015 #3
    If I sweep Vds from 20V to 0V with vGS = 0, then iDS starts at 60pA, then it falls very slowly, then at vDS = 1V or so, it quickly rises to 400pA. (see picture)
    If vGS is not 0 but lower than Vt, then iDS starts at 54 pA, then it falls until vDS = 1 with some slope, then after vDS = 1, it quickly falls to 0 pA or so.

    If vGS is greater than Vt, then iDS starts at the saturation current, then it stays constant, then it falls to 0. This part I understand.

    I would say that I also understand the part where vGS is not 0 but lower than Vt. For a given vGS, the leakage current increases with increasing vDS. It's common sense.
    But for vGS = 0, I do not understand what is happening or where to look.

    Attached Files:

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    Last edited: Dec 1, 2015
  5. Dec 1, 2015 #4


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  6. Dec 1, 2015 #5
    Ok, thanks.
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