# Phase Sweep

1. Dec 1, 2016

### Pencil123

I am trying to create a phase sweeper at 31.4KHz(and constant 5V) for a small antenna array that consists 2 antennas. If I can create 2 signals with a frequency difference < 1Hz it's okay too(It will be nearly same) as long as I can control that difference because I need to change phase at a constant velocity which I can change.

It's okay too if you can tell me how to do it with arduino or LPC1769(I have one) or with a PIC(I can always buy one!). I tried to do it with arduino and created phase shifts with resolution of 5 degrees. But unfortunately the maximum frequency I got was 172Hz!

My last resource would probably be making a rc phase shift oscillator with an opamp which has 18 RC stages. But then I need to control it from arduino so it'll be a very big and complex circuit.

Thanks!

2. Dec 1, 2016

### Staff: Mentor

I don't have anything specific in mind, but ...

Does it matter if the amplitude of the phase-shifted signal changes a little as ɸ is varied?

You'd be happy with 180° shift in steps of 5°, because an inverter could account for the rest of the ±180° range?

You say "signals", but do you mean sinusoids? Square-waves would be easier.

Is it okay if the ɸ-shifted signal has a bit of added noise?

3. Dec 1, 2016

### Baluncore

Are the antennas electromagnetic or ultrasonic, receive or transmit?
Is the 31.4 kHz the carrier frequency ?
Is this beam steering or sweeping?
Is 1 Hz the 360° phase sweep frequency ?

4. Dec 1, 2016

### Pencil123

Does it matter if the amplitude of the phase-shifted signal changes a little as ɸ is varied?

It doesn't matter if amplitude changes if iit is a little change. if it is a big change I would need to change it back to 5V with something else.

You'd be happy with 180° shift in steps of 5°, because an inverter could account for the rest of the ±180° range?

I said it's okay 180° shift in steps of 5° because it doen't have to be that sensitive. But of course it'd be nicer with smaller steps.

You say "signals", but do you mean sinusoids?

Square waves. Right now I'm using an arduino to create it(DC) but I can use a sensitive 555 or something to create 2 signals(with slightly different frequency <1Hz).

Is it okay if the ɸ-shifted signal has a bit of added noise?

I don't know if noise would be a problem. I think as long as it doesn't effect the frequency it's OK but it's just a guess.

Are the antennas electromagnetic or ultrasonic, receive or transmit?

Antennas are elctromagnetic, transmit.

Is the 31.4 kHz the carrier frequency ?

It's not a carrier frequency. I won't send a signal with it. It'll be always constant at 5V 31.4KHz.

Is this beam steering or sweeping?

I will steer beams for following an object with constant speed.

Is 1 Hz the 360° phase sweep frequency ?

I said 1Hz because when I was trying to do this I connected 2 frequency generators at 31.4KHz(I was trying to see if my antennas steer to a direction at a constant phase). But when I connected generators to an oscillator I saw that there was a frequency difference(<1Hz) and the phase diffrence was always changing. It was the exact thing I want so I was happy. For a second. Then I realised that frequency difference wasn't stable. Phase sweep became faster or slower.

Thanks!

5. Dec 2, 2016

### Baluncore

How about something like an 8.0384 MHz master oscillator feeding two 8 bit binary dividers. They divide by 256 to give 31.4 kHz square waves.
But the master clock to one of those dividers passes through a pulse swallower circuit that hides one clock pulse each time it gets a command. That swallow command can be sent 256 times per second by either a processor or a timer chip. The divider output phase will then be retarded by 360°/256 degrees per clock pulse swallowed. The divided frequencies will differ by 1 Hz. The two dividers can have a common reset to set a zero phase difference. Digital Pulse swallowing circuits are reasonably simple, usually only a couple of flip-flops and a gate or two.

You could use less bits in the dividers to get bigger phase steps per swallow.
8 bits, divide by 256, gives 1.406° per swallow. Use 8.0384 MHz clock.
7 bits, divide by 128, gives 2.812° per swallow. Use 4.0192 MHz clock.
6 bits, divide by 64, gives 5.625° per swallow. Use 2.0096 MHz clock.

6. Dec 2, 2016

### Baluncore

Here is an untested guess at a pulse swallowing phase shift circuit.
There are three inputs. 1. The master clock. 2. A positive edge on the swallow pulse input will swallow only one clock pulse. 3. A high voltage on the synchronise phase input resets the counters to zero phase. When synchronise phase goes low the counters begin to advance together.

The 74HC4040 ripple counters should do the job OK. They could be replaced with 74HC4520 synchronous counters in applications where ripple counter phase noise is a problem.
The D-F/F used to synchronise the counter resets with the clock should not be needed for high master clock rates with small phase steps.

7. Dec 2, 2016

### Staff: Mentor

Antennas that are resonant at 31kHz would be huge. What exactly are you trying to do? And using square waves, is not consistent with EM antennas.

Also, FYI -- it is better to use the PF Quote/Reply feature when quoting other users. Just click the "Reply" link to quote a user's whole post, or use a mouse click-drag across the user's text that you want to quote, and click Reply after you have finished the click-drag selection.

8. Dec 2, 2016

### Baluncore

Small, multi-turn inductive loop antennas can be capacitively tuned to 31.4KHz.
The Q could be quite high, so it is unlikely that 3'rd harmonic radiation would be a problem.

9. Dec 2, 2016

### Staff: Mentor

Good point. But I've never considered small rod/solenoid antennas for TX, only for RX. Have you seen them use in transmitter applications? Although, if the OP is just wanting to do low-power experimenting, maybe the choice of frequency and choice of antenna are good things...

10. Dec 2, 2016

### Baluncore

Cave and underground mine communication systems use even lower frequencies.

31.4 kHz is in the middle of the band used by switching power supplies and the few remaining horizontal sweep oscillators for CRTs.
A navigation system employing 31.4 kHz would use phase comparison.
Metal detectors use similar frequencies to penetrate the surface.

11. Dec 3, 2016

### Pencil123

Thank you for your response! I am going to test it on wednesday. I'll post the results once I tested it. Also there is a symbol that I don't know on schematics. The one connected to the top pin of the top 74HC02 and to the data pin of the lower left 74HC74(a cross inside a circle). What does that represent?

Last edited: Dec 3, 2016
12. Dec 3, 2016

### Baluncore

That ⊕ is my shorthand for Vcc = +5V = logic high. There is an error, where the unusual Vcc is on the 74HC02 NOR gate, the unused terminal should be connected to ground, not Vcc. I was asleep when I drew the diagram and must have been dreaming of AND gates.

If the 8.0384 MHz clock is divided by 2^15 it gives ( 8038400 / 32768 ) = 245.3125 Hz. So if you extend the 'fast' output divider by a few binary stages, to generate 245.3125 Hz, then you can use that to feed the swallow control. That will give you close to a 1 Hz difference frequency.

13. Dec 3, 2016

### Pencil123

There is something that I'm wondering. 74HC74's Q' pin connected to the other 74HC74's CLR but then doesn't Q' always become high no matter what? Even if there is a pulse swallow signal, neither Q will be high. Am I thinking wrong?

Edit: I just made a simulation in proteus and it worked. Can you explain me why? Also circuit works pretty well!(in simulation) Thank you very much! You are a lifesaver.

Last edited: Dec 3, 2016
14. Dec 3, 2016

### Baluncore

The first D-F/F takes the asynchronous positive edge of the swallow command and holds it until the second D-F/F synchronises it with the master clock. The duty cycle of the swallow command input is irrelevant, only the positive edge is important.

Follow the swallow logic round the loop this way;
1. The positive edge of the swallow command loads the first D-F/F with D1 which is always tied high, so then Q1 goes high.
2. The next master clock pulse transfers that Q1=high into the second D-F/F so Q2 goes high and blocks the flow of the master clock through the NOR to the 74HC4040 counter/divider 'slow channel'.
3. But that Q2=high means NotQ2 will be low, which is fed back to the negative logic Clear of the first D-F/F, cancelling the swallow state and preparing it for the next swallow command.
4. The next master clock transfers that low state into the second D-F/F, which ends the swallow and removes the asynchronous clear from the first D-F/F. That is why it can only swallow one clock cycle per command.

15. Dec 7, 2016

### Pencil123

It worked perfectly! Thank you very much! I learned lots of things from that.