Problem with CD4040B counter simulation in PSpice

[milanetf]

TL;DR

Problems with results of DAC R-2R converter with CD4040B ripple counter

I am trying to make a DAC R-2R ladder with CD4040B counter. Output should be a staircase but it is just a straight line in my simulation. I am probably doing something wrong as I am not that experienced with Spice so I would appreciate any help. I tried it without counter(just attached four clocks on every bit) and it worked just as supposed.

 

[berkeman]

Welcome to the PF.

I don't know if it's the source of the problem, but it is bad practice in general to leave CMOS inputs floating. In real circuits, it generates noise and increases the power consumption of the device with the floating CMOS input.

So in your circuit you should at least tie off the RESET input low (inactive). Then check the counter outputs to be sure they are counting like you expect when you supply the clock input.

 

[milanetf]

Hi,thanks for your reply. I did as you said for the reset input, but the simulation stays the same. I am not sure what is the problem as this circuit really isn't that complicated. Thanks for the advice anyway! :)

 

[berkeman]

What do you see when you monitor the input and output signals on the CD4040? Is it counting?

 

[berkeman]

Also, what is the power supply for the CD4040? Are you just feeding a 1V square wave into the clock input? That will not meet the Vih spec of the CD4040...

 

[milanetf]

I know that it should have a power supply but there is no other input on this symbol, except INPUT and RESET. I have a component and it has a clk input and a supply voltage but here in spice,this symbol does not have anything else. I guess I am missing something :D

 

[berkeman]

What do you get when you double-click on the CD4040 symbol in your PSPICE schematic? Here is what I get in MicroCAP 9:

(also, what happens when you feed in the clock and monitor the LSB output? Try different amplitude clocks?

 

[milanetf]

I noticed that even when I leave both input floating the simulation stays exactly the same as before,it still shows that straight line at the same voltage level,even more confusing,maybe that will help you understand what is going on,because I am stuck for days at this.
Double clicking on symbol is just editing properties. When clicking od edit PSpise model this pop up. Also when I feed the clock and monitor LSB it is also just a voltage level(straight line) at 2.6V.

 

[tech99]

Also when I feed the clock and monitor LSB it is also just a voltage level(straight line) at 2.6V.

How come it is 2.6V? I thought these CMOS devices needed 3 to 18 volts supply and the high output should be very close to this, such as 2.95V. I am not sure you have correct operating voltage, but I am sorry I don't know how to specify that in SPICE.

 

[Baluncore]

Screenshot_3.png shows power pins can be made visible.
Connect the supplies.

2.65 volts is near the middle of 0V and 5V supplies.

Maybe you could simplify your circuit.
Set supply voltage and all signal inputs to 0V and 5V.
Generate a 1kHz clock and view it.

Then simulate a CD4001 NOR gate. Use it to invert the 1 kHz clock.
When that works, add the CD4040 to the simulated circuit.

I cannot make you a Pspice example circuit because I use LTspice.
Logic functions in LTspice default to levels of 0 and 1 volt. Expect surprises.

 

[Tom.G]

Try adding a battery for the supply voltage.
Battery "-" to GND (or the Gnd symbol) and to a network you name VSS
Battery "+" to a network you name VDD (VDD for CMOS devices, VCC for bipolar devices)

The VSS and VDD don't have to go anywhere other than the supply (battery), naming them should get Pspice parts libraries to recognize it as a supply.

Make the clock signal amplitude from 0V to the battery voltage.

EDIT: This is from the ORCAD manual but probably very similar to PSpice.

To display invisible power pins
Invisible power pins always appear in the part editor. The
method by which you display invisible power pins in the
schematic page editor determines whether you can connect
wires and other connectivity objects to them
On a part instance
1 Select the part in the schematic page editor.
2 From the Edit menu, choose Properties.
3 Find the Power Pins Visible property column on the
property editor Parts tab and select the check box, then
close the property editor.

Cheers,
Tom

 

[berkeman]

I noticed that even when I leave both input floating the simulation stays exactly the same as before,it still shows that straight line at the same voltage level,even more confusing,maybe that will help you understand what is going on,because I am stuck for days at this.

I did a quick test in MicroCAP 9 SPICE, and got closer to having it working. I'm still not clear why the output voltage levels are too high even when I run the CD4040 at VDD = 5V and use a 5V pulse input source into the clock. I use a DC voltage source on the Reset input to verify that there is no clock output signal when RESET is HIGH = 5V, and the output signal is the clock /2 when RESET is LOW = 0V. I'll try to figure out where the output signal offset is coming from later today if I have time. I mainly use SPICE for analog simulations, so I haven't seen this offset before.

Run a Transient Analysis:

 

[milanetf]

Thanks a lot guys for your replies, I had to work the whole day today so I didnt have any time to test your solutions. I will try it first thing tomorrow and let you know how it went. Once again,thank you!

 

[Baluncore]

In post #8 there is screenshot 2. That is the CD4040 model definition. Some code is missing.
Can you attach the entire model definition for the CD4040 as a file.txt
Then I can find out how the model actually works.

 

[milanetf]

Yes,I just noticed that. Here it is:

 

[Tom.G]

when I run the CD4040 at VDD = 5V

At 5V supply the output drive is only 0.51mA. Even at 15V there is only 3.4mA available. The ladder network needs to be much higher impedance to avoid exceeding the chip drive capability.

See pg.3 of the datasheet at:
https://www.onsemi.com/pub/Collateral/MC14040B-D.PDFor pg 3-68 of datasheet here:
https://www.ti.com/lit/ds/symlink/cd4040b.pdf
Cheers,
Tom