PWM Controller period and duty cycle questions

AI Thread Summary
The discussion focuses on the behavior of a PWM controller using a 555 timer IC, particularly regarding the effects of varying resistance and supply voltage on duty cycle and period. Increasing the potentiometer (POT) resistance decreases the duty cycle, as the switch remains closed longer to compensate for increased voltage. When the supply voltage is raised while keeping the POT resistance constant, the period decreases, indicating an increase in switching frequency due to altered voltage thresholds between 1/3 and 2/3 of VCC. The interaction between the charging and discharging currents and the output voltage swing on pin 3 complicates the relationship between these variables. Overall, understanding these dynamics requires a deeper exploration of the 555 timer's operation.
Steve Collins
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I've carried out some testing on a PWM controller using a 555 timer IC (see attached for circuit diagram) and I am having a little trouble understanding the results.

When the POT resistance is increased the duty cycle decreases. As I understand it, when the resistance is increased the voltage increases (V= IR). So to bring the voltage back down the switch stays closed for longer which means that the duty cycle decreases.


When the POT is left at a constant resistance and the source voltage is increased why does the period decrease and the duty cycle remain constant?

Does this mean that the switching frequency is increasing? If it is, why?
 

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I think you need to read up on how the 555 works. Basically when configured as an oscillator the cap is charged and discharged between 1/3 and 2/3rd of the supply voltage.

The pot has three terminals and (together with the diodes) is set up so that one "side" of the pot is used for the charge phase and the other for the discharge phase. Moving the pot centre tap transfers resistance from the time constant for one phase to the other - so the mark space ratio changes.

Changing the supply voltage alters the "distance" (more correctly the "voltage difference") between 1/3rd VCC and 2/3rd VCC so the frequency will change. For example

At VCC=9V the switching thresholds would be at 3V and 6V a difference of 6-3=3V.

At VCC=10V the switching thresholds would be at 3.33V and 6.66V a difference of 3.33V which is greater. So the capacitor has to charge and discharge "further" before it switches and the frequency will be slightly slower.

Edit: I note that you say the period increases when the source voltage is increased. Is that correct? If so then note that the charging and discharging current also depends on the voltage across the pot which in turn depends on the output voltage swing on pin 3. That also changes with changing VCC. There are a lot of possible interactions. It's been a while since I used a 555 and I forget which dominates.
 
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Thanks for your reply and guidance.

I will look into the 555 with the information you have given me in mind.
 
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