Spikes in CMOS Inverter transients

[reddvoid]

I am simulating cmos inverter in CADENCE
I am getting a sharp spike when output is going from low to high
and spike became more amplified like when i made rise time and fall time of input rectangular pulse signal very low . . .can somebody explain why this happening ?

 

[phyzguy]

A current spike or a voltage spike?

 

[NascentOxygen]

I am simulating cmos inverter in CADENCE
I am getting a sharp spike when output is going from low to high
and spike became more amplified like when i made rise time and fall time of input rectangular pulse signal very low . . .can somebody explain why this happening ?

With the CMOS inverter, isn't there a point during transition where both of the devices are conducting simultaneously? With static input, one or other of the transistors is fully OFF, but during transition from one state to the other, for a moment both transistors are partly ON, hence the rush of current you observe.

 

[reddvoid]

its a voltage spike
like this

sry, its happening when output is going from high to low

 

[NascentOxygen]

It would be helpful if you were to indicate 0V and +Vcc levels.

I understand this is for an unbuffered inverter?

Your output's load is currently an open circuit? Try a reasonable load, and see how this improves. Say, 1MΩ for starters. Just guessing, but it could well be feedthrough of the input.

 

[jim hardy]

I notice this Cadence tutorial connects a 50 f(emto?)F capacitor to their cmos inverter for an output load.
Might that be its purpose?

See page 22 ff...
http://scholar.cu.edu.eg/?q=hmostafa/files/cadencetutorial.pdf

Figure 3 on page 38 shows a similar spike caused by changing transistor size.

Wow that's quite a simulation...

just a guess

old jim

 

[reddvoid]

snapshots

this is the circuit

simulation

Yes output was floating,
then i tried 5fF load
and resistive load from 1k to 1M.
still getting spikes in all the simulations .

different cap loads

 

[phyzguy]

These spikes are caused by parasitic capacitance between the inverter input and output. Most of it is the gate-drain capacitance in the MOS transistor. When the output is high and the input transitions from low to high, the voltage across this parasitic capacitance cannot change instantaneously, so some of the input step gets coupled to the output. It is a real effect. The spike is larger on the rising edge of the input because the PMOS G-D capacitiance is larger than the NMOS (I think - you could check this in the SPICE model by looking at the Cgd parameter).

 

[NascentOxygen]

You are seeing it because it's meant to be there. If a problem you might see it reduce if you were to increase the risetime of the gate voltage, so it rises less sharply. The height of the spike is probably limited (clamped) by a pn junction to Vcc. Adding load capacitance is not viable.

 

[Baluncore]

I agree with phyzguy, it is capacitive coupling.

The threshold voltages of the two mosfets must be chosen so there is little through current during a transition.
When the input goes high, the upper mosfet should turn off before the lower mosfet turns on.

During the short period that both mosfets are off, the inverter input is being capacitively coupled directly to the output load by the C_GD of both mosfets in parallel.

The ratio of transition spike energy is related to the ratio of mosfet C_GD.
The effective C_GD is voltage dependent and highest during transition.

 

[reddvoid]

got it :) Thanks guys .