Split clock signal (provided by oscillator)

In summary: RF or microwave system.That depends. Measurements instruments usually use a 10 MHz sine as a external reference signal and will have a "ref in" and "ref out" connector at the back. In precision instruments (which I presume is what we are talking about here, not much point locking several instruments to the same oscillator otherwise) the oscillator is a loop and they can lock to an external reference as long as it is reasonably close to the internal reference.I don't think I've ever come across a digital clock being used as an external reference (not even in say backplanes of rackmounted equipment); it just seems like an unnecessary complication when you can so easily do clock recovery (and generate
  • #1
Tom48
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hi,

i was wondering how its possible to split a clock signal provided by an oscillator in order to use it to drive multiple devices with this one split clock signal.
Let's assume we have a kind of USB device (like an USB stick), that gets its clock signal from an oscillator.
Let's say i would like to provide the same clock signal to multiple USB devices of the same kind (to synchronize them). Would it be possible to take the already build in oscillator out, split the clock signal of this oscillator, amplify it and then provide this clock signal to all devices so they all have the same clock signal?
How would i amplify the clock signal? Could i just use an operational amplifier with no feedback to amplify the clock signal?

At the moment i have no certain device, I am just curious how this could be done?

Thanks a lot!
 
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  • #2
If the digital clock source (Fosc) is external on the master clocked device then a simple clock buffer chip using that signal will work. Some devices have a internal oscillator with an output pin to drive external devices with a programmed configuration option for a external clock that may not be accessible on a production USB stick.
3.3v device: http://www.ti.com/product/CDCLVC1112
 
  • #3
nsaspook said:
If the digital clock source (Fosc) is external on the master clocked device then a simple clock buffer chip using that signal will work. Some devices have a internal oscillator with an output pin to drive external devices with a programmed configuration option for a external clock that may not be accessible on a production USB stick.
3.3v device: http://www.ti.com/product/CDCLVC1112
thanks for your reply!
Im indeed talking about devices that all have internal oscillators only.
So i had to remove the internal oscillator from the device first.
After i would clock multiple devices of the same kind with one shared oscillator.
But i guess i first had to amplify the given clock signal somehow in order to clock mutiple devices with it. (because its going to be to weak after the signal split)
Could i just amplify this signal using an omp amp (open loop gain configuration)?

thanks!
 
  • #4
Tom48 said:
Could i just amplify this signal using an omp amp (open loop gain configuration)?

thanks!

Assuming the clock is a digital signal.
Because of transmission line effects/fanout (current drive capability) and the need for clean,fast rise/fall times on the clock a proper digital driver would be better for any signals greater than maybe 1 MHz.
 
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  • #5
nsaspook said:
Assuming the clock is a digital signal.
Because of transmission line effects/fanout (current drive capability) and the need for clean,fast rise/fall times on the clock a proper digital driver would be better for any signals greater than maybe 1 MHz.

That depends. Measurements instruments usually use a 10 MHz sine as a external reference signal and will have a "ref in" and "ref out" connector at the back. In precision instruments (which I presume is what we are talking about here, not much point locking several instruments to the same oscillator otherwise) the oscillator is a loop and they can lock to an external reference as long as it is reasonably close to the internal reference.

I don't think I've ever come across a digital clock being used as an external reference (not even in say backplanes of rackmounted equipment); it just seems like an unnecessary complication when you can so easily do clock recovery (and generate a digital clock) from a sinewave
 
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Likes Tom48 and nsaspook

1. What is a split clock signal?

A split clock signal is a type of clock signal that is generated by an oscillator and then divided into multiple signals with different frequencies. This is often used in digital circuits to provide synchronization between different components.

2. How is a split clock signal created?

A split clock signal is created by an oscillator, which is an electronic circuit that generates a periodic waveform. This waveform is then fed into a frequency divider circuit, which splits the original signal into multiple signals with different frequencies.

3. Why is a split clock signal used?

A split clock signal is used to provide synchronization and timing control in digital circuits. By dividing the original clock signal into multiple signals, different components can operate at different frequencies while still being synchronized with each other.

4. What are the advantages of using a split clock signal?

One advantage of using a split clock signal is that it allows for more efficient use of resources. By dividing the original clock signal, different components can operate at their optimal frequencies, which can improve overall performance and reduce power consumption.

Another advantage is that it reduces the amount of electromagnetic interference (EMI) in a circuit. By distributing the clock signal, the EMI is spread out and can be easier to filter, resulting in a more reliable and stable circuit.

5. Are there any drawbacks to using a split clock signal?

One potential drawback is that the split clock signal may introduce jitter, which is a variation in the timing of the signals. This can cause errors in the circuit and may need to be carefully managed and compensated for.

Another drawback is that designing and implementing a split clock signal can be complex and may require additional components and circuitry. This can increase the cost and complexity of a circuit design.

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