Stop & Wait DLC System: State Machine & Timing

[VinnyCee]

Homework Statement

Consider the operation of a Stop and Wait DLC system as shown below. The system is using 2-bit sequence numbers.

[PLAIN]http://img210.imageshack.us/img210/4496/hw2problem3diagram.jpg

<a> Show the state machine from initial state (SN = 00, RN = 00) to the state (SN = 11, RN = 11).

<b> Show the timing of each state transition in the state machine.

Homework Equations

None to speak of really.

The Attempt at a Solution

<a>

[PLAIN]http://img262.imageshack.us/img262/1881/2bitstopandwaitstatemac.jpg

Does that look right?



<b>

I have no idea. There are duplicate times t_9 and t_{11} - is that an error?

Maybe it's just a list (or table) of what state the machine (i.e. - SN = 01, RN = 10... etc.) is at each time t such that t_0\,\le\,t\,\le\,t_{13}?

Please help!

 

[VinnyCee]

The duplicate times t_9 and t_{11} are errors. Ignore the first of each since they don't really change the state of the machine anyways.