Engineering Transistor circuit low-frequency response

[favq]

Homework Statement

This problem is adapted from the book "Transistor Circuit Techniques" by G. J. Ritchie.

Given the following circuit:

(1) Calculate the AC gain of the circuit, for frequencies where C₁ and C₂ can be considered as short-circuits.

(2) Sketch the low-frequency response due to capacitors C₁ and C₂ (assuming that C₁ = C₂).

Homework Equations

The Attempt at a Solution

(1) Below is the AC model for the circuit, shorting the capacitors:

In the calculations below, i_{b_1}, i_{c_1} and i_{e_1} are respectively the base, collector and emitter currents of TR1, and i_{b_2}, i_{c_2} and i_{e_2} are respectively the base, collector and emitter currents of TR2.
v_{in} can be expressed as the sum of the voltages across r_{\pi_1} and R_4:
v_{in} = i_{b_1}(r_{\pi_1}+(\beta+1)R_4)
Similarly, v_{mid} can be expressed as the sum of the voltages across r_{\pi_2} and R_6:
v_{mid} = i_{b_2}(r_{\pi_2}+(\beta+1)R_6)
Applying KCL to the node labeled v_{mid}:
i_{c_1}+\dfrac{v_{mid}}{R_3}=-i_{b_2}
v_{mid}=-R_3(i_{b_2}+i_{c_1})=-R_3(i_{b_2}+\beta i_{b_1})
Equating both expressions for v_{mid}:
i_{b_2}(r_{\pi_2}+(\beta+1)R_6) = -R_3(i_{b_2}+\beta i_{b_1})
Solving for i_{b_2}:
i_{b_2} = \dfrac{-R_3\beta i_{b_1}}{R_3+r_{\pi_2}+(\beta+1)R_6}
v_{out} can be expressed as the voltage across R_6:
v_{out} = i_{e_2}R_6=(\beta+1)i_{b_2}R_6
Plugging in the expression for i_{b_2}:
v_{out} = \dfrac{-\beta(\beta+1)R_3R_6 i_{b_1}}{R_3+r_{\pi_2}+(\beta+1)R_6}
Making i_{b_1} = \dfrac{v_{in}}{(r_{\pi_1}+(\beta+1)R_4)}:
v_{out} = \dfrac{-\beta(\beta+1)R_3R_6 v_{in}}{(R_3+r_{\pi_2}+(\beta+1)R_6)(r_{\pi_1}+(\beta+1)R_4)}
Finally, calculating the AC gain, A=\dfrac{v_{out}}{v_{in}}:
A=\dfrac{v_{out}}{v_{in}} = \dfrac{-\beta(\beta+1)R_3R_6}{(R_3+r_{\pi_2}+(\beta+1)R_6)(r_{\pi_1}+(\beta+1)R_4)}

(2) This is where I'm having the most trouble. I'm not sure what the author meant by "low frequency response".
In the book, the author has used the term "low frequency response" referring to how the gain behaves as a function of frequency when the frequency is very low, so that the capacitors can't be considered as short circuits.
So, I assume that I should sketch the gain as a function of frequency, for low values of frequency. In order to try to do that, I redid the AC model to include the capacitors C1 and C2:

In the above model, I named the source voltage v_s, and v_{in} is now just the voltage that appears in the base of TR1. The relationship between v_s and v_{in} is the following:
v_{in} = \dfrac{r_{in}v_s}{r_{in} + \dfrac{1}{j\omega C_1}}
Where:
r_{in}=R_1\parallel R_2\parallel \left (r_{\pi_1}+(\beta+1)\left (R_4+R_5\parallel\dfrac{1}{j\omega C_2}\right )\right)
Now, the gain is A_{\omega}=\dfrac{v_{out}}{v_s}. From the expression above:
A=\dfrac{v_{out}}{v_{s}}=\dfrac{v_{out}}{v_{in}}\dfrac{r_{in}}{r_{in} + \dfrac{1}{j\omega C_1}}
where \dfrac{v_{out}}{v_{in}} is like the expression found for the AC gain before, but with R_4 replaced by R_4+R_5\parallel\dfrac{1}{j\omega C_2}.
A_{\omega}=\dfrac{v_{out}}{v_{s}} = \left ( \dfrac{-\beta(\beta+1)R_3R_6}{(R_3+r_{\pi_2}+(\beta+1)R_6)\left (r_{\pi_1}+(\beta+1) \left (R_4+R_5\parallel\dfrac{1}{j\omega C_2} \right ) \right )}\right ) \left (\dfrac{r_{in}}{r_{in} + \dfrac{1}{j\omega C_1}}\right )

I'm not sure how to proceed from here. At first, I think I can conclude that, as the frequency becomes very low, the term \dfrac{r_{in}}{r_{in} + \dfrac{1}{j\omega C_1}} approaches zero, so the gain approaches zero for very low frequencies. As the frequency increases, the gain approaches the value of the AC gain that I found in (1).

Thank you in advance.

 

[Paul Colby]

This looks plausible to me. My only question is why is the two stage gain expression negative. Each stage provides negative gain so two minuses should be a positive?

 

[The Electrician]

This looks plausible to me. My only question is why is the two stage gain expression negative. Each stage provides negative gain so two minuses should be a positive?

The TR2 stage is an emitter follower; its gain is not inverting.

 

[Paul Colby]

Ah, yes that it is, that it is.

 

[Paul Colby]

So, the effect of the cap on the input is as you've written it. As the second caps impedance becomes significant the gain of the first stage should increase. Is there a way to chose $R_5$ to partially offset the loss of low frequency gain from $C_1$?

 

[favq]

So, the effect of the cap on the input is as you've written it. As the second caps impedance becomes significant the gain of the first stage should increase. Is there a way to chose $R_5$ to partially offset the loss of low frequency gain from $C_1$?

Thank you for the reply. To try to answer your question:
The gain is basically formed by two factors:
A=\left ( \dfrac{v_{out}}{v_{in}} \right ) \left (\dfrac{r_{in}}{r_{in}+\dfrac{1}{j\omega C}} \right )
where v_s is the input voltage, r_{in} is the input impedance at TR1's base, and v_{in} is the voltage at TR1's base.
Suppose the frequency is low. If I make R_5 very big, that will increase the input impedance r_{in}, so the factor r_{in} / \left ( r_{in} + \dfrac{1}{j\omega C} \right ) will approach 1. However, the factor \dfrac{v_{out}}{v_{in}} will decrease (since now TR1's emitter impedance is higher), and will approach a minimum value of:

\dfrac{-\beta(\beta+1)R_3R_6}{(R_3+r_{\pi_2}+(\beta+1)R_6)(r_{\pi_1}+(\beta+1)(R_4+R_5))}.

On the other hand, suppose I try to make R_5 very small. In that case, \dfrac{v_{out}}{v_{in}} will increase, approaching a maximum value of:

\dfrac{-\beta(\beta+1)R_3R_6}{(R_3+r_{\pi_2}+(\beta+1)R_6)(r_{\pi_1}+(\beta+1)R_4)}

However, since r_{in} will decrease, then r_{in} / \left ( r_{in} + \dfrac{1}{j\omega C} \right ) will decrease too.
It's not very clear to me how I should choose R_5.
Thank you in advance.

 

[Paul Colby]

I think $R_5$ is chosen mainly to set the operating point for $Tr_1$ so one can get maximal headroom on the output signal.

 

[rude man]

For low frequencies there are two capacitors determining the gain.
C2 sets a finite gain even at dc, as you point out. The overall gain is essentially reduced from R3/R4 to R3/(R4 + R5). But C1 forms a 1st order low pass network. At dc the overall amplifier gain is thus zero.

 

[LvW]

For low frequencies there are two capacitors determining the gain.
C2 sets a finite gain even at dc, as you point out. The overall gain is essentially reduced from R3/R4 to R3/(R4 + R5). But C1 forms a 1st order low pass network. At dc the overall amplifier gain is thus zero.

I rather think that C1 - together with the transistors input resistance - forms a 1st order HIGHPASS.
Hence, both capacitors have an high-pass effect - however with different time constants due to different associated resistors.

 

[rude man]

I rather think that C1 - together with the transistors input resistance - forms a 1st order HIGHPASS.
Hence, both capacitors have an high-pass effect - however with different time constants due to different associated resistors.

I rather think you're correct - I meant high-pass for C1.

But C2 does not form a high-pass cutoff the way C1 does. C2 does not establish zero gain at zero frequency; C1 does.
The Laplace gain for C1 alone (input to base) is T₁s/(T₁s +1) with T₁ = (R1 || R2)C1 whereas for C2 alone it's (base to output) of the form (T₂s + a)/(T₃s + b), with gain = R3/(R4+R5) at zero freq. instead of zero.

 

[LvW]

I rather think you're correct - I meant high-pass for C1.

But C2 does not form a high-pass cutoff the way C1 does. C2 does not establish zero gain at zero frequency; C1 does.
The Laplace gain for C1 alone (input to base) is T₁s/(T₁s +1) with T₁ = (R1 || R2)C1 whereas for C2 alone it's (base to output) of the form (T₂s + a)/(T₃s + b), with gain = R3/(R4+R5) at zero freq. instead of zero.

Yes - no dubt about this.
Nevertheless - C2 causes a highpass effect. The gain increases with frequency in the "critical" frequency region.
Of course - as you wrote - it is not a highpass with a zero. On the other hand - not too important.
It`s only - more or less - a question of classification or convention.