Vhdl Temperature simulation help

[keith03]

Vhdl help!

Please help...This is driving me crazy. I am just trying to setup a simple comparing component. The code compiles fine, but the simulation is WAAAAAYY off. could somebody please check this? Thanks

--Temprature high or low
--
library ieee;
use ieee.std_logic_1164.all;
entity thermostat is
port
(
data_in_mux : in std_logic_vector (3 downto 0);
set_main : in std_logic_vector (3 downto 0);
data_out : out std_logic_vector (1 downto 0)
);
end thermostat;
--
architecture behave of thermostat is
begin
process (set_main, data_in_mux)
begin

if (set_main < data_in_mux) then
data_out <= "00";
elsif (set_main > data_in_mux) then
data_out <= "11";
else data_out <= "01";

end if;
end process;
end behave;

 

[keith03]

I figured it out, the code was fine, but the simulation tool was not appropriatly set.

 

[gaNo__X]

hello everyone!
i have to do a sychronous 8-bit up/down counter.
to the momment i am here. My entity is right.
As for the up/down control, we have the inputs up and down,
and If up = 1 it counts up, if down =1 it counts down and if both of them are 1 it does nothing.

can anyone help?

this is what i have done so far.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_down_counter is
port (
count ut std_logic_vector (7 downto 0);
data ut std_logic_vector (7 downto 0);
up,down :in std_logic; -- up_down control for counter
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;

architecture rtl of up_down_counter is

signal count :std_logic_vector (7 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (up XOR down = '1') then
if(up = '1') then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
end if;
end process;
count <= count;
end architecture;