Full Adder using a 3-to-8 Decoder in VHDL

[michael_mke]

I need to design a full adder using a 3-to-8 decoder.

I have the code for the 3-to-8 decoder but don't know how to use it as a full adder.
Please help. Thanks

//3-to-8 Decoder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Decoder is
   port (
      A : in unsigned(2 downto 0);
      Y : out unsigned(7 downto 0));
end Decoder;

architecture Logic1 of Decoder is

   type TableType is array (0 to 7) of unsigned(7 downto 0);

   constant Table : TableType :=
      ( "00000001", "00000010", "00000100", "00001000",
        "00010000", "00100000", "01000000", "10000000");

begin

   Y <= Table(to_integer(A));

end Logic1;

 

[anorlunda]

A full adder is a full adder. It doesn't matter if one of the inputs comes from a decoder.

How would you make a full adder with unknown inputs?