Voltage Swing for NMOS: Digital ICs by Jan M. Rabaey

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Discussion Overview

The discussion revolves around the voltage swing in NMOS transistors as described in Jan M. Rabaey's "Digital Integrated Circuits." Participants explore concepts related to voltage charging, the behavior of source followers, and the implications of overdrive voltage in the context of digital integrated circuits.

Discussion Character

  • Technical explanation
  • Conceptual clarification
  • Debate/contested

Main Points Raised

  • One participant questions why a node x charges to Vdd - Vtn1 instead of Vdd, seeking clarification on the underlying principles.
  • Another participant explains that when A and B are connected to Vdd, M1 acts as a source follower, and if the source X rises above Vdd–Vth, M1 will turn off, stopping the rise of X.
  • Concerns are raised about the voltage drop across M2 being zero, with a participant asserting that this drop is the overdrive voltage (Vds) and questioning the implications for current flow.
  • A different perspective is provided, suggesting that the voltage drop across M2 depends on the output load current and the Ron of M2, which can be negligible for low currents.
  • One participant notes that if Vds is less than Vov, the NMOS would enter linear mode, which is described as unfavorable, although the reasons for this are not fully explored.
  • Another participant mentions that the voltage drop increases when the drain drives the gate of another MOSFET, indicating a practical application of the discussed concepts.

Areas of Agreement / Disagreement

Participants express varying levels of understanding and agreement on the behavior of NMOS transistors, particularly regarding voltage drops and operational modes. Some points remain contested, particularly around the implications of Vds and the conditions under which M2 operates.

Contextual Notes

There are unresolved assumptions regarding the definitions of terms like overdrive voltage and the specific conditions under which the NMOS operates in different modes. The discussion does not clarify the full implications of these terms in the context of the circuit described.

jaus tail
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Voltage swing for nmos is Vdd - Vth? How?
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Ref: Digital Integrated Circuits by Jan M. Rabaey

I have trouble understanding two things:
1) Why will x charge to Vdd - Vtn1 and why not Vdd?
2) If x in left charges to Vdd - Vtn1, then in right also it would charge to Vdd - Vtn1... so Vy would charge to Vdd - Vtn1 - Vtn2... so why have they written the swing as vdd - Vtn1 and why not Vdd - Vtn1 - Vtn2?
 
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1. When A and B are connected to Vdd, M1 is a source follower, if the source X then rises above Vdd–Vth, M1 will turn off and so X will stop rising

2. Both M1 and M2 are source followers with their source voltages set between common and Vdd–Vth. The voltage dropped across M2 can be zero so Vth is not cascaded.
 
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Thanks. I understood the 1 part. But not the second part. How will drop across M2 be zero. Drop across M2 is overdrive voltage, right? I.e Vds.

Vx can be Vdd - Vth. If Vy also becomes Vdd-Vth, then there will be no current flow as Vds = 0. No potential difference so no current flow.
 
Think of an NMOS FET as a variable resistor, with Ron set by Vgs. The voltage drop across M2 = Vsd, will depend on output load current multiplied by Ron of M2. For low currents it will be only a few mV, so close to zero.
 
Ok, but if Vds is less than Vov, then the mosfet would go in linear mode, right? That's not a favorable mode (I don't know why though. Most switch mode should be cut off or saturation)
 
244748
 
The voltage drop increases when the drain is used to drive the gate of another Mosfet as shown in left part of above pic. Thanks for this :)
 

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