# Voltage Swing for NMOS: Digital ICs by Jan M. Rabaey

• jaus tail
In summary, the conversation discusses the operation of NMOS FETs and the voltage drop across them when used as source followers. It explains that the voltage drop across M2 can be close to zero due to the current flow and Ron of M2. It also mentions that when the voltage drop is less than the overdrive voltage, the FET will go into linear mode.
jaus tail
TL;DR Summary
Voltage swing for nmos is Vdd - Vth? How?

Ref: Digital Integrated Circuits by Jan M. Rabaey

I have trouble understanding two things:
1) Why will x charge to Vdd - Vtn1 and why not Vdd?
2) If x in left charges to Vdd - Vtn1, then in right also it would charge to Vdd - Vtn1... so Vy would charge to Vdd - Vtn1 - Vtn2... so why have they written the swing as vdd - Vtn1 and why not Vdd - Vtn1 - Vtn2?

1. When A and B are connected to Vdd, M1 is a source follower, if the source X then rises above Vdd–Vth, M1 will turn off and so X will stop rising

2. Both M1 and M2 are source followers with their source voltages set between common and Vdd–Vth. The voltage dropped across M2 can be zero so Vth is not cascaded.

jaus tail
Thanks. I understood the 1 part. But not the second part. How will drop across M2 be zero. Drop across M2 is overdrive voltage, right? I.e Vds.

Vx can be Vdd - Vth. If Vy also becomes Vdd-Vth, then there will be no current flow as Vds = 0. No potential difference so no current flow.

Think of an NMOS FET as a variable resistor, with Ron set by Vgs. The voltage drop across M2 = Vsd, will depend on output load current multiplied by Ron of M2. For low currents it will be only a few mV, so close to zero.

Ok, but if Vds is less than Vov, then the mosfet would go in linear mode, right? That's not a favorable mode (I don't know why though. Most switch mode should be cut off or saturation)

The voltage drop increases when the drain is used to drive the gate of another Mosfet as shown in left part of above pic. Thanks for this :)

## 1. What is voltage swing in NMOS?

Voltage swing in NMOS refers to the difference in voltage between the high and low states of a digital signal. In other words, it is the range of voltage levels that can be used to represent digital information in an NMOS circuit.

## 2. How is voltage swing determined in NMOS?

Voltage swing is determined by the supply voltage and the threshold voltage of the NMOS transistor. The supply voltage sets the upper limit of the voltage swing, while the threshold voltage determines the lower limit.

## 3. Why is voltage swing important in digital ICs?

Voltage swing is important in digital ICs because it affects the noise margin, power consumption, and speed of the circuit. A larger voltage swing allows for better noise immunity and faster switching, but it also consumes more power.

## 4. What are the factors that affect voltage swing in NMOS?

The main factors that affect voltage swing in NMOS are the supply voltage, threshold voltage, load capacitance, and channel resistance. The choice of transistor size and circuit design also play a role in determining the voltage swing.

## 5. How can voltage swing be optimized in NMOS circuits?

Voltage swing can be optimized by carefully choosing the supply voltage, transistor size, and circuit design to balance noise immunity, power consumption, and speed requirements. Techniques such as cascoding and supply voltage scaling can also be used to improve voltage swing in NMOS circuits.

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