Check the User Guide documentation for the part you're
using. e.g. for the Spartan 3 / Spartan 3A DCMs:
http://direct.xilinx.com/bvdocs/userguides/ug331.pdf
q.v. pages 61...
Using Digital Clock Managers (DCMs)
Summary
Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan-3
Generation FPGA applications (Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, and
Spartan-3A DSP families). Primarily, DCMs eliminate clock skew, thereby improving
system performance. Similarly, a DCM optionally phase shifts the clock output to delay the
incoming clock by a fraction of the clock period. DCMs optionally multiply or divide the
incoming clock frequency to synthesize a new clock frequency. The DCMs integrate
directly with the FPGA’s global low-skew clock distribution network.
Introduction
DCMs integrate advanced clocking capabilities directly into the FPGA’s global clock
distribution network. Consequently, DCMs solve a variety of common clocking issues,
especially in high-performance, high-frequency applications:
• Eliminate Clock Skew, either within the device or to external components, to
improve overall system performance and to eliminate clock distribution delays.
• Phase Shift a clock signal, either by a fixed fraction of a clock period or by
incremental amounts.
• Multiply or Divide an Incoming Clock Frequency or synthesize a completely new
frequency by a mixture of clock multiplication and division.
• Condition a Clock, ensuring a clean output clock with a 50% duty cycle.
• Mirror, Forward, or Rebuffer a Clock Signal, often to deskew and convert the
incoming clock signal to a different I/O standard—for example, forwarding and
converting an incoming LVTTL clock to LVDS.
• Any or all the above functions, simultaneously.
