RC circuit, discharge with digital signal from FPGA

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Discussion Overview

The discussion revolves around measuring the charge time of an RC circuit using an FPGA, specifically focusing on how to discharge the capacitor without premature discharge for subsequent inputs in a 4x4 matrix keypad application.

Discussion Character

  • Exploratory, Technical explanation, Debate/contested

Main Points Raised

  • One participant outlines the task of measuring charge time and discharging the capacitor for a matrix keypad, seeking advice on circuit design.
  • Another participant questions whether the task requires external circuitry or if it can be accomplished solely with the FPGA, suggesting that resistor and capacitor values may need adjustment for safe operation.
  • A different participant proposes using a GPIO pin connected to an NPN transistor to facilitate the discharge of the capacitor, including a resistor to limit current.
  • The original poster acknowledges the lack of limitations on external circuits but expresses a preference to explore options that do not require them.

Areas of Agreement / Disagreement

Participants have not reached a consensus on the best approach to discharging the capacitor, with differing opinions on the necessity of external components and the methods to achieve the desired functionality.

Contextual Notes

There are unresolved considerations regarding the specific resistor and capacitor values needed to ensure safe operation within the FPGA's rated current limits.

ttsky
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Hi all,

my task is to measure the charge time of an RC circuit with a counter using FPGA, once the cap is charged, i must discharge it again for next input. Idea is to discharge it with a signal from FPGA, but what sort of circuit would allow this without discharging the cap prematurely?

if it helps, the circuit is for a 4x4 matrix keypad, row and colums tied to resistors and a cap, each button press should produce a diffrent charge time, i need the caps to be discharged before next keystroke.


Thanks

∫Aziz∫
 

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I'm not sure I understand your stated task. Are you saying that you need to do this without any external supporting circuitry for the FPGA or do you intend on using external components?
You can use the FPGA alone, but your resistor values will need to be increased and the cap value lowered such that the FPGA I/O pin can be used as a discharge by pulling the cap low from a tri-state output (probably through a low value resistor to limit the current). To do this you need to set the resistor and cap values that the current in the discharge side is below the rated sink current of the I/O pin for the selected part. Search through the app notes of the various FPGA manufacturers about using their parts for A/D or with special inputs dedicated as comparator - I know Lattice has notes that describe this use.
 
You can use a GPIO - directly to a Base on an NPN, with a resistor to limit current. Cap ( to be discharged) -- Resistor -- Transistor Collector -the Transistor Emitter to ground.
 
Thank you for reply, There are no limitations on external circuits, however if i don't have to then i wont, i will explore those options and post an update soon.

thanks
 

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