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Homework Help: 4-Bit Shift Register on Verilog

  1. Apr 18, 2010 #1
    This is basically a continuation of a previous problem I submitted. I worked out the previous problem, now I need to figure out another problem. This 4-bit shift register won't load the number I am trying to load. I have exhausted every possible error where it could be wrong. I commented lines out to see if I could pinpoint it, but I cannot seem to find out why it won't load my number. This was done using Verilog.

    If anyone can figure out where the typo is so I can load the register with a value, that would be most helpful.

    Code (Text):
    module t_Shift_Register_4_str;
    wire [3:0] a_par;
    reg [3:0] i_par;
    reg s1,s0,msb_in,lsb_in,clk,clear,select;
    Shift_Register_4_str m0(a_par,i_par,s1,s0,msb_in,lsb_in,clk,clear,select);
    initial #100 $finish;
    initial begin clk=0; forever #10 clk=~clk; end
    initial fork
    #0 i_par=4'b0100; clear=1; select=1;
    #0 s1=1'b1; #20 s1=1'b1; #40 s1=1'b0; #60 s1=1'b0;
    #0 s0=1'b1; #20 s0=1'b0; #40 s1=1'b0; #60 s0=1'b1;
    #0 msb_in=1'b1;
    #0 lsb_in=1'b1;
    join
    endmodule

    module Shift_Register_4_str (A_par,I_par,Select,s1,s0,MSB_in,LSB_in,CLK,Clear);
    output [3:0] A_par;
    input [3:0] I_par;
    input [1:0] Select;
    input s1,s0,MSB_in,LSB_in,CLK,Clear;
    assign {Select[1],Select[0]} = {s1,s0};
    stage ST0 (A_par[0],A_par[1],LSB_in,I_par[0],A_par[0],Select,CLK,Clear);
    stage ST1 (A_par[1],A_par[2],A_par[0],I_par[1],A_par[1],Select,CLK,Clear);
    stage ST2 (A_par[2],A_par[3],A_par[1],I_par[2],A_par[2],Select,CLK,Clear);
    stage ST3 (A_par[3],MSB_in,A_par[2],I_par[3],A_par[3],Select,CLK,Clear);
    endmodule

    module stage (i0,i1,i2,i3,Q,select,CLK,Clr);
    input i0,i1,i2,i3;
    output Q;
    input [1:0] select;
    input CLK,Clr;
    wire mux_out;
    Mux_4_x_1 M0 (mux_out,i0,i1,i2,i3,select);
    D_flip_flop M1 (Q,mux_out,CLK,Clr);
    endmodule

    module Mux_4_x_1 (mux_out,i0,i1,i2,i3,select);
    output mux_out;
    input i0,i1,i2,i3;
    input [1:0] select;
    reg mux_out;
    always @ (select or i0 or i1 or i2 or i3)
    case ({select})
    2'b00: mux_out = i0;
    2'b01: mux_out = i1;
    2'b10: mux_out = i2;
    2'b11: mux_out = i3;
    endcase
    endmodule

    module D_flip_flop (Q,D,CLK,Clr);
    output Q;
    input D,CLK,Clr;
    reg Q;

    always @ (posedge CLK or negedge Clr)
    if(~Clr) Q<=1'b0; else Q<=D;
    endmodule
     
  2. jcsd
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