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A question on MOS transister.

  1. Jun 2, 2010 #1

    Looking at the cross section of MOS transistor, substrate tap(nMOS) and well tap(pMOS) are done on heavily doped regions. Basically, GND is connected to p+ in nMOS, and VDD is connected to n+ in pMOS.. What could be a problem if we don't have heavily doped regios for substrate and well tappings and VDD and GND are directly connected to n- well and p- substrate ?
    Last edited: Jun 2, 2010
  2. jcsd
  3. Jun 2, 2010 #2
    The reason for heavy doping in the well regions is to establish an *ohmic contact*. All semiconductor devices such as diodes, bjt, IC, etc. use this method. At an interface where a semiconductor must be connected to the outside world through a lead or bond wire (layer to layer interconnect), a rectifying contact won't work. When a semiconductor is bonded to a metal, a Schottky diode junction can be formed if the semicond doping is not heavy enough.

    Such a diode junction will block a signal in 1 direction, something we may not want. Visualize a bjt or FET. The lead wire into the collector or drain can form a diode. Likewise for the lead wire in the emitter or source. We now have 2 diodes in opposite directions, meaning that no substantial current can be realized. Heavy doping makes the metal-semicond interface non-rectifying, aka "ohmic".

    As far as tying the substrate to ground (actually tied to the source), I've seen cases where the substrate is not tied. A good book on CMOS fabrication will explain in detail the reasons for doing so. I hope I've helped.

    Last edited: Jun 2, 2010
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