"I had a 0.1uF capacitor in parallel with the solar cell, should I leave it connected between signal<O> going into the PIC or no?"
Leave it connected across the solar cell terminals
themselves and it'll be fine. If you really end up with
a serious problem of the analog signal changing too
rapidly or getting high frequency noise coupled into your
circuit then you could look at more intensive
capacitive+resistive filtering connections.
But for the moment that doesn't seem to be a problem and
leaving it across the solar cell terminals is just fine for
just a little bit of filtration.
I also had another idea that I'd like to ask you about.I'm not sure if it'll work or not but here goes..
<S>--<Scmitt trigger IC>---<R1>---<base of NPN transistor>
<emitter of NPN>--ground
<S>--<R2>--<collector of NPN>--<PIC analog input>
I'm not sure what value to pick for R2 but R1 could be=(Vcc-Vbe)/Ibase; Vbe~0.7V, Ibase-->from the spec sheet of 2n3904(those are the ones I have handy).
The schmitt trigger IC would be powered by Vcc as V+ and ground as V-.
The <S> would be the signal from the solar cell or Vref and that same signal goes
into the collector of the NPN transistor through a high resistance R2.
The way I understand it,when Vref would be greater than 2.5V there would be a low signal at the output of the schmitt trigger which would cause the NPN transistor to stay off and so the Vref going into the PIC would be high.If Vref is less than 2.5V there would be a high signal at the output of schmitt trigger IC which would turn the NPN transistor on and cause a drain at the collector so the PIC would receive a low voltage.
Do you think this arrangement might work?If it does I might try it this way as well.Could you please recommend
a Schmitt trigger IC I could use for this application.
A good schmitt trigger for use between +5V
power supply and 0V ground logic would be the
74HC14, I'd guess that you could get them cheaply
in quantity one from DigiKey, Mouser, Newark, et. al.,
and that the datasheets would be available from
www.ti.com[/url], [url]www.fairchild.com[/URL], etc.
They are INVERTING S.T. gates, though, FYI, so use
two in series or just realize/accept the signal inversion.
[url]http://www.fairchildsemi.com/pf/MM/MM74HC14.html[/url]
[URL]http://www.onsemi.com/PowerSolutions/product.do?id=74HC14DR2G[/URL]
R1 being between a CMOS +5V logic schmitt trigger
output and the base of an NPN transistor whose emitter
is grounded would be having about +5V across it when
the S.T. output is HIGH.
The S.T. can drive 10 TTL load equivalents, and is
specified with the absolute maximum current output per
pin of 25mA. So choosing 3mA of base current to the
transistor should be a reasonable compromise. As you
said, V_BE is around 0.7V for a typical single small
signal NPN, so 5-0.7 = 4.3V, and so about 1.5k R1 would
give you about 3mA of base current when the S.T. is high.
As for the rest:
<S>--<R2>--<collector of NPN>--<PIC analog input>
<+VREF>--<R2>--<collector of NPN>--<PIC analog input>
<+5V>--<R2>--<collector of NPN>--<PIC analog input>
Well I don't see too much point in any of the options there
but your logic with the transistor operation is mostly
correct.
If the S.T. output is low, the transistor will have
I_BASE = 0, the NPN will be OFF / non-conducting, and
there will be basically a high resistance between
emitter and collector. Since the collector goes to the
PIC input, the PIC will effectively see a signal input
equal to whatever is connected to the PIC input
ignoring the transistor which acts like an open circuit
between its C and E when it's OFF. If you had
<S>--<R2>---<PIC INPUT> where <S> is the
solar cell, it'd be the same as having the solar cell go
to the PIC IN through R2 when the transistor is OFF.
If you have <+5V>---<R2>---<PIC INPUT> then
when the transistor is OFF the PIC would see
+5V through R2 resistance on its input.
The similar would be true if the source was <VREF>
assuming <VREF> is some fixed positive voltage
between +2.5 and +5VDC.
When the S.T. output is HIGH, transistor base gets 3mA
current, the collector emitter path goes to some fairly
low resistance, and assuming R2 is more than a few
hundred ohms, the collector voltage would be getting
down into the range of less than +0.5VDC so the PIC
would see a low voltage signal.
However if what you want is a LOGIC level
at the PIC input, why not just reconfigure the PIC
input as a LOGIC input and not an ADC analog input.
Then you could just do:
<+SOLAR CELL>---<ST IN>
<ST OUT>---<PIC DIGITAL IN>
and you have a logic input to the PIC that is
0 if the solar cell terminal goes from dark low voltage
to illuminated higher voltage and transitions to
output somwhere between +2.3 and +3.1VDC.
1 when the solar cell was illuminated but goes dark
and transitions from a high positive voltage output
lessening to somewhere between +2.0 and +0.9VDC.
If you want that inverted logically you could just connect
another ST gate in series with the first
and then have the opposite
<1> <0> sense of those logic levels appearing at the PIC.
If you really wanted the solar cell analog voltage to appear
at the PIC ADC analog input, I don't see too much point
in adding the S.T. and NPN...
Now if you wanted you could tie the solar cell analog
to the PIC ADC, AND tie the solar cell analog to some
S.T. type of circuit whose logic output goes to some
DIFFERENT PIC logic interrupt input pin configured to
give you an software interrupt when there is a logic level
change based on the solar cell voltage so your
software could go out and measure the actual voltage
of the ADC at that moment or something.
But if you want to work with analog signals and you
had something like an 8 bit ADC with
+VREF = +VIN_MAX = +5V, then
ADC 255 = +5.00VDC in
ADC 127 = +2.50VDC in
ADC 063 = +1.25VDC in
etc. so you can just choose some number of ADC
reading as a threshold for saying "light" or "dark"
and then it is a small matter of choosing whatever
ADC number best suits the light level you're trying to
detect. It shouldn't be very necessary to use
external comparators, schmitt triggers, attenuators,
amplifiers, etc. to make the level of the signal that
corresponds to 'light' and 'dark' some particular value
since the ADC in the PIC can already (with some
limited resolution) tell you the value anywhere between
+VREF and 0V.