I have a linear model of a phase detector (phase lock loop) represented by the block diagram below. It is designed to maintain zero difference in phase between the input carrier signal and a local voltage controlled oscillator.(adsbygoogle = window.adsbygoogle || []).push({});

Phase demand→Ka→F(s)→K/s→Phase output

F(s) = 10(s+10)/(s+1)(s+100)

We want to minimise the steady state error for a ramp change in the phase information signal.

Can anyone help determine the limiting value of the gain KaK = Kv in order to maintain a stable system.

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# Calculating gain of a phase detector

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