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Cmos circuit design

  1. May 20, 2014 #1
    when designer design new circuit, they think whats the requirement

    step I
    1)power dissipation should be less
    2)raise time and fall time should be less
    3)propagation delay time should be less
    4)size should be small as possible

    step II

    1) how can we reduce power dissipation in cmos circuit?

    - we have to decrease voltage or current in circuit
    - we have to decrease resistance in circuit

    2) how can we reduce raise time and fall time?
    -which parameter depend on raise and fall time
  2. jcsd
  3. May 20, 2014 #2


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    Science Advisor

    Do you want high speed or low power? You must select a compromise.

    Use smallest possible geometry active elements to get less capacitance and less charge storage.

    Clock the circuit as slowly as possible. Design so minimum outputs and inputs change each cycle.

    Use the lowest possible supply voltage, but make sure there is no through current when both pull up and pull down outputs conduct.
  4. May 20, 2014 #3
    1) how can we reduce power dissipation in cmos circuit
  5. May 31, 2014 #4


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    Science Advisor

    Most digital designers don't have to worry much about things like rise/fall time and prop delay. They just make sure the process they are using is fast enough then they focus on the logical design (using a hardware description language).

    Baluncore told you how to reduce power dissipation.

    If you're actually designing custom CMOS layout (unlikely) then you reduce capacitance by making devices small and using high level metal for routing when possible. You reduce resistance by making wide wires (although this makes capacitance more... there is a compromise, as Baluncore said).
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