Designing a Half Pulse Shaping Circuit Using Cadence: Expert Help Needed

[shaikss]

Hi,

I need to design a circuit which gives positive half cycle of sine wave when logic 1 is given as input and negative cycle of sine wave when logic 0 is input. Please let me know how to design the same using cadence.

 

[Floid]

Sounds like you need a few pieces:

A circuit that generates a sine wave

A half wave rectifier

A transistor switch that controls whether you are doing positive or negative half wave rectification With some googling I think you can find enough about each of those stages to build the circuit you want.

 

[sophiecentaur]

How good does this half sine wave need to be?
Why does it need to be sinusoidal?
There are a load of similar questions that need to be asked if you want the best answer to your needs.

 

[berkeman]

Hi,

I need to design a circuit which gives positive half cycle of sine wave when logic 1 is given as input and negative cycle of sine wave when logic 0 is input. Please let me know how to design the same using cadence.

Do you have any experience programming microcontrollers (uCs)? One of the easiest ways to do this is to program a PIC or similar uC with the waveform data, and have it output the waveform via an R2R ladder DAC circuit (followed by a simple opamp lowpass filter of course).

 

[shaikss]

Do you have any experience programming microcontrollers (uCs)? One of the easiest ways to do this is to program a PIC or similar uC with the waveform data, and have it output the waveform via an R2R ladder DAC circuit (followed by a simple opamp lowpass filter of course).

I want to simulate the same in cadence for one of my module.
For one of my modules, I need to design half pulse shaping circuit.The input is the digital data - logic 1 and logic 0. The output should be positive cycle of sine wave when logic 1 is present and negative cycle when logic 0 is present.

 

[berkeman]

I want to simulate the same in cadence for one of my module.
For one of my modules, I need to design half pulse shaping circuit.The input is the digital data - logic 1 and logic 0. The output should be positive cycle of sine wave when logic 1 is present and negative cycle when logic 0 is present.

You already said all of that in your Post #1. You have received several suggestions so far in our replies here in this thread. How do you now plan on designing this circuit?

 

[sophiecentaur]

I want to simulate the same in cadence for one of my module.
For one of my modules, I need to design half pulse shaping circuit.The input is the digital data - logic 1 and logic 0. The output should be positive cycle of sine wave when logic 1 is present and negative cycle when logic 0 is present.

If you are not more forthcoming with specific information you will not get any satisfactory answers. Reading between the lines, I conclude that you may have been told that a 'raised cosine' pulse shape is good for minimising intersymbol interference.
This link may be of some help. But without more help (some background, if you are totally confused by the task, perhaps(?)) we can't help much more.