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Detector of even numbers in logic circuit

  1. Feb 15, 2015 #1
    1. The problem statement, all variables and given/known data
    I need to make a circuit that detects even numbers.
    Need to find the equation for F when input A and B are both even.

    Input A: Word of 5 -bit signed representation in complement 2.
    Input B: Word of 3 -bit signed representation in complement 2.

    2. Relevant equations
    for B:
    000 = 0 (even)
    001 = 1
    010 = 2 (even)
    011 = 3
    100 = -4 (even)
    101 = -3
    110 = -2 (even)
    111 = -1

    For A:
    same as B but with 5 bits.

    00000 = 0 (even)
    00001 = 1
    00010 = 2 (even)
    00011 = 3
    00100 = 4 (even)
    00101 = 5
    00110 = 6 (even)
    00111 = 7
    ....
    .......
    11111 = -1

    3. The attempt at a solution

    I am just wanting to know the steps on how I start this.

    Do I do Karnaugh for both inputs then join both equation together?
     
  2. jcsd
  3. Feb 15, 2015 #2

    lewando

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    What feature of a number represented in binary (either unsigned or 2's complement) allows you to tell that it is odd or even? Don't need to convert it to decimal... There is something all even binary numbers have in common that allows you identify them as even.
     
  4. Feb 15, 2015 #3
    I realized that binary ending with a 0 = even and binary ending with 1 = odd.

    So basically its F = /A/B ??
     
  5. Feb 15, 2015 #4

    lewando

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    You are not interested in all of the binary digits of A or B. Just the least significant binary digit.
     
  6. Feb 15, 2015 #5
    How do I make my logic circuit to check only the least significant binary digit?
     
  7. Feb 15, 2015 #6
    if input B least significant bit = 0 then its an even number.
    if input A least significant bit = 0 then its an even number.

    If A and B = 0 then its an even number and F = 1

    but how do I actually write this in an equation with gates?
     
  8. Feb 15, 2015 #7

    phinds

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    Why do you have "If A and B = 0 then its an even number and F = 1" as a separate condition?

    Why do you have the first two statements as independant statements? They are NOT true taken as stand-alone statements.

    How do you combine all 3 statements in to one statement?
     
  9. Feb 15, 2015 #8
    Sorry my english is not my primary language I did not meant to split it up in 2 condition, just that when A and B = 0 then the output is 1.
     
  10. Feb 15, 2015 #9
    Here are my Kmap for input A and B.
     

    Attached Files:

  11. Feb 15, 2015 #10

    phinds

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    You had it right in your statements and now you are complicating it. Why?
     
  12. Feb 15, 2015 #11

    lewando

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    Maybe this is the root of the problem. When you have to draw an actual circuit, how will you represent a 5-bit binary number? A 3-bit binary number? What will you draw?
     
  13. Feb 15, 2015 #12
    I don't know, but here the final equation:

    F = /B0 * /A0
     
  14. Feb 15, 2015 #13

    lewando

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    That looks right.
     
  15. Feb 15, 2015 #14

    phinds

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    Really? How about when both numbers are odd?
     
  16. Feb 15, 2015 #15
    if both numbers are odd it would output 0 since I am only checking the least significant bit. and the least significant bit in odd numbers will be 1. and 1 * 1 would output 0 since there are NOT gates in both inputs or am I wrong ?
     
  17. Feb 15, 2015 #16

    phinds

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    Sorry, I got to thinking we were doing an adder output. You and lewando are both right and I'm wrong. Now *I* was over thinking it :smile:
     
  18. Feb 15, 2015 #17
    No worries man, you helped me a lot today and these past days, I really appreciate it man. I just wish my teachers were a little bit better :(
     
  19. Feb 15, 2015 #18
    one last thing :)
    If an inverter has a 2 ns propagation delay , an AND logic gate has a 5 ns propagation delay and an OR gate has a 4ns delay , what is the maximum period required by the circuit in order to update the output F ?

    would I just do 2ns x 2 sicne I have 2 inverter and 5ns x1 since I only have one then add up everything ? = 4+5=9ns ?
     
  20. Feb 15, 2015 #19

    lewando

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    From a time-flow perspective, the inverters are operating in parallel of each other and the AND gate is in series with the inverters. You are correct to not consider a nonexistant OR gate. 9 ns would be incorrect. Rethink.
     
  21. Feb 15, 2015 #20
    2+5= 7 then

    I
     
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