Differential limiting amplifier

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Discussion Overview

The discussion revolves around the analysis of a differential limiting amplifier circuit, focusing on its behavior under different input conditions and the implications of various component values. Participants explore both DC and AC analysis, as well as the effects of biasing and saturation on the amplifier's performance.

Discussion Character

  • Technical explanation
  • Mathematical reasoning
  • Debate/contested

Main Points Raised

  • One participant expresses difficulty in understanding the differential limiting amplifier circuit and requests a step-by-step analysis.
  • Another participant suggests determining the quiescent state of the circuit without an input signal, assuming familiarity with basic transistor theory.
  • A detailed DC analysis is presented, involving equations for base currents and voltage drops across various components, with assumptions about matched transistors.
  • Further exploration of the output behavior is proposed when a signal is applied incrementally to one of the inputs, with a focus on observing instantaneous voltage levels.
  • A participant notes the neglect of capacitors and the need to switch to AC small signal analysis, presenting equations that relate input and output voltages.
  • Concerns are raised about the bias arrangements and the implications of small resistor values, suggesting that the circuit operates in saturation and produces a square wave output.
  • Another participant corrects an earlier oversight regarding the supply voltage for certain resistors, indicating that both transistors are operating within their linear range.

Areas of Agreement / Disagreement

Participants express differing views on the applicability of small signal analysis versus large signal behavior, with some indicating that the circuit is deeply in saturation while others suggest it can still function as a small signal amplifier. The discussion remains unresolved regarding the overall behavior of the amplifier under varying conditions.

Contextual Notes

Limitations include assumptions about transistor matching and the neglect of certain circuit elements like capacitors, which may affect the analysis. The discussion also highlights the complexity of biasing arrangements and their impact on circuit performance.

mmzaj
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HI

i know that the circuit attached to this thread is a differential limiting amplifier , and the collector of Q2 acts as a current source , but other than that , i can't get my mind around it ! P1 is the input , P5 is the output , and Vcc is +12 connected to the 27 R .

could someone please walk me step by step on how to analyze (understand) this freakin Amp !
 

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Let's see if we can help you work this out on your own. First of all, can you determine what the state of the circuit is at quiescence (that is, with no input signal)? I'm assuming you're familiar with basic transistor theory, here.
 
well , here is a detailed DC analysis :

5=[tex]I_{B_{1}}R_{3}+V_{BE}+(\beta_{1}+1)R_{5}(I_{B_{1}}+I_{B_{2}})[/tex]

and

5=[tex]I_{B_{1}}R_{4}+V_{BE}+(\beta_{2}+1)R_{5}(I_{B_{1}}+I_{B_{2}})[/tex]

but because [tex]R_{3}=R_{4}=:R[/tex] obviously :

[tex]I_{B_{1}}=I_{B_{2}}=:I_{B}[/tex]

(( and [tex]\beta_{1}=\beta_{2}=:\beta[/tex] assuming Q1 , Q2 are matched ))

and

[tex]5-0.7=(R+2(\beta+1)R_{5})I_{B}[/tex]

hence

[tex]I_{B}=\frac{4.3}{R+2(\beta+1)R_{5}}[/tex]

applying KVL to the outer loop :

[tex]12=2\beta R_{2}I_{B}+V_{CE_{1}}+2(\beta+1)I_{B}R_{5}[/tex]

[tex]12=2\beta R_{2}I_{B}+V_{CE_{2}}+ \beta I_{B} R_{6}+2(\beta+1)I_{B}R_{5}[/tex]

we have [tex]I_{b}[/tex] , and we can find [tex]V_{CE_{1}},V_{CE_{2}}[/tex] , and the rest of Is and Vs .
 
Nicely done.

Now, what happens to the output when you apply a signal which gradually increases in, say, +0.5 V increments to P2? We'll bypass P1 for now, since we just want to observe what happens at various instantaneous input voltage levels.

(I'll be off to bed now, so take your time!)
 
sadly , i don't have a scanner in order to upload my work , so i have to post it using latex , and man , it's sooo painful !

anyways , i'am not sure i got it right here , i neglected the effect of the capacitors , and didn't switch to AC small signal analysis !

let V @ P2 be [tex]V_{i}[/tex]

then [tex]V_{i}=V_{BE_{1}}+(\beta +1)R_{5}(I_{B_{1}}+I_{B_{2}})[/tex]

[tex]5=I_{B_{2}}R_{4}+V_{BE_{2}}+(\beta_{2}+1)R_{5}(I_{B_{1}} +I_{B_{2}})[/tex]

=>[tex]5=I_{B_{2}}R_{4}+V_{i}[/tex]

but [tex]5=I_{B_{1}}R_{3}+V_{i}[/tex]

=> [tex]I_{B_{1}}=I_{B_{2}}=:I_{B}[/tex]

now

[tex]V_{CE_{2}}=12-(2\beta R_{2}+\beta R_{6}+2(\beta +1)R_{5})I_{B} = 12-\frac{(2\beta R_{2}+\beta R_{6}+2(\beta +1)R_{5})(5-V_{i})}{R_{3}}[/tex]

let [tex]\frac{2\beta R_{2}+\beta R_{6}+2(\beta +1)R_{5}}{R_{3}}=:X[/tex]

[tex]V_{E}=2(\beta +1)R_{5}I_{B}=\frac{2(\beta +1)R_{5}(5-V_{i})}{R_{3}}[/tex]

let [tex]\frac{2(\beta +1)R_{5}}{R_{3}}=:Y[/tex]

[tex]V_{C_{2}}=V_{E}+V_{CE_{2}}=12+(Y-X)(5-V_{i})[/tex]

i don't have the data sheet of the 2N3904 - yet!- in order to obtain [tex]\beta[/tex] , but clearly X>Y ... =>

[tex]V_{o} =V_{C_{2}}=A+gV_{i}[/tex] where A is a DC offset , and g is some sort of a gain !

bare with me friend , i'am a detailed person !
 
vk6kro said:
However, you need to look at the bias arrangements to see the real picture.
Those 1K resistors are very small and will hold the transistors deeply in saturation.

So, the small signal analysis doesn't really apply. This is a large signal circuit and will tend to poduce square wave output.
Not quite true. Both bases are approx the same voltage (but there should be a pot to balance small offsets). The voltage across R5 (820 ohms) is about 4.3 volts, so current is about 5.2 mA. This current is split between the two transistors equally. The voltage across R2 (27 ohms) is about 0.14 volts, and across R6 (820 ohms) is about 2.15 volts. So Q2 and by inference Q1 are both in the middle of their linear range. Good small signal amplifier.
 
Yes, sorry. I missed the 5V supply for the 1 Ks.
 

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