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Voltage offset differential amplifier

  1. Feb 10, 2017 #1
    Hi all!

    I am trying to simulate a differential amplifier in LTSpice but I'm having some troubles.
    First, I would like to know if you could suggest me some "basic", scholastic, MOSFET and BJT model, like the 1N4148 for diodes.

    Secondly I designed this:

    Practically when I get the drain output I have a big amplification but with a HUGE DC offset: 12 volts about!!!
    Do you know why?Did I mistaken somehitng?

    Moreover I don't remember a thing from my electronics studies: should R1 be linked to ground or to V1?

    Thank you very much
  2. jcsd
  3. Feb 10, 2017 #2
    Perhaps it's better this way
    ― the drain of M1 ought to be kept at the same voltage as M2.

    It's better to use a dual matched pair of MOSFET in one package as M1 and M2.
    Last edited: Feb 10, 2017
  4. Feb 11, 2017 #3
    Your solution makes sense, I have some thoughts though:
    First, I would like to use as less resistors as possible, like if it was an IC amplifier.
    Secondly, I would like to know why my circuit offsets the voltage so much. This is basically the easiest form of differential amplifier, so there must be a problem I cannot recognize.


    This is from the Sedra-Smith; as as you see I replaced the current source with the mirror, but the offset is still there.

    What I think is that there is some problem either with transistors model, or ltspice itself. In fact I simulated an exercise from Sedra-Smith:


    Which results are Rd=5k and Rs=3.25; and LTSpice gives different values for Id and Vd! The model I used is:

    .model M1 NMOS(Vto=0.7 Kp=100u L=1u W=32u)

    Is the model wrong?
  5. Feb 11, 2017 #4
    It may well be the channel length modulation effect (neglected in the textbook but not in LTspice) to blame. In ICs, MOSFETs with very low channel modulation must be used, otherwise all the mirrors would work wrong. With your differential amplifier, I would first try to decrease the positive supply so as to make the drain potentials (left and right) equal when both the inputs are grounded.
  6. Feb 11, 2017 #5


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    You are operating the amplifier in open loop. What are you measuring the huge DC offset voltage relative to.

    Ground will be quieter and heat the resistor half as much.
  7. Feb 11, 2017 #6


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    Your output voltage, (drains of M2 and M6 ?), is centred about +12 volt above ground because that is the voltage on the drain of M5, (and on the gates of the symmetrical p-channel mirror).
  8. Feb 11, 2017 #7
    Oh right, my bad, that is the bias point; I've avoided that bypassing the output with a capacitor. But now an abvious questions arises: in real multistage opamp, where the output of one stage is the input of the next stage, is the dc component kept in each stage, it doesn't seem so to me, does it? Moreover, even if it does, is the output always bypassed with a capacitor in real cases?
  9. Feb 11, 2017 #8
    As pointed out by Baluncore we never use this type of circuit without some sort of a negative feedback to "set" DC conditions.
    No, your model is just fine. I for Rd = 5k and Rs = 3.25k get Id≈400μA in LTspice
    You can also use this model
    .model n VDMOS (Vto=0.7 Kp=3.2m)
  10. Feb 11, 2017 #9


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    Here is an output stage added to the differential front end.
    Attached is an LTspice file diff-amp.asc. Remove the .txt extension to view or run it.

    Attached Files:

    Last edited: Feb 11, 2017
  11. Feb 12, 2017 #10

    Oh I don't know, this circuit keeps on yielding 54 uA :/

    Thank you very much, I got your point :)
  12. Feb 12, 2017 #11
    Change NMOS name into M1 . Upper M1 is a transistor designation number not the sim MODEL.
  13. Feb 12, 2017 #12
    Thank you, got it!
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