Digital Electronics Boolean Reduction

[DethRose]

Digital Electronics Boolean Reduction! Help Please

Ok i need to figure out how to reduce this I've been working on it for 2 days straight and can't figure it out...please help...its due tommorow




(ab)(\overline c + \overline d)+(a+b)(\overline c \overline d)

 

[mcfetridges]

well good question. I expanded that equation and then threw it in a k-map. I got the exact expanded equation back. I would say that that equation is the simplest form. Hopefully someone can back me up. my kmap was sum of m(4,8,12,13,14).

 

[DethRose]

it can't be the same equation because i was given it for homework like that and have to do a whole project on simplifying it. I need to make the circuit using the least amount of logic gates.

Heres the question i was given in class:

Design a traffic light circuit using the following criteria

1. The light will be green when both lanes A and B are occupied but C and D are not both occupied.
2. The light will be green when either A or B is occupied while C and D are both vacant.

So the formula i have at the beginning of the post is what i created after reading the criteria.

 

[NeutronStar]

So what was the answer?

1. The light will be green when both lanes A and B are occupied but C and D are not both occupied.
2. The light will be green when either A or B is occupied while C and D are both vacant.

I actually wrote a Visual Basic program to simulate your logic in your opening post and it does work as you say. However, I couldn't figure out how to reduce it either.

So now I'm curious what the reduction logic is, and how was it arrived at?

I tried using DeMogan's laws, and various other logic rules but I couldn't reduce it either. Somehow though I have a gut feeling that it can be reduced. So now you have me curious.

 

[dduardo]

I get the same equation back

 

[NeutronStar]

So the formula i have at the beginning of the post is what i created after reading the criteria.

If you created this formula what make you so sure that it can be reduced?

I went over your criteria and came up with the exact same formula. Unusually if there's a way to reduce it I'll notice it at that stage of development. I really can't see any obvious way to reduce it.

I even went to a logic circuit simulator on the web and typed in the logic circuit (see attached figure).

I thought that maybe I could see a way to reduce it by just looking at the circuit but I can't see anything there either.

The NOT gates in my circuit were used simply because the simulator would only provide NAND and NOR gates. So they aren't really a part of the main logic. Also the dual outputs represent the central OR in your formula. I just didn't feel like bothering to put in the additional NOR gate with yet another inverter so I left the two outputs hanging. The circuit works as you describe, but again I can't see any obvious way to reduce it.

 

[dduardo]

If you use a 8to1 MUX with ABC as the select lines and D as the input then you only need one inverter.

 

[NeutronStar]

Reducing gates or chips?

If you use a 8to1 MUX with ABC as the select lines and D as the input then you only need one inverter.

Actually I wasn't even thinking in terms of using anything like a multiplexer. I was thinking just in terms of reducing primitive gates. Heck, you can always reduce anything to a single chip if you're willing to use an FPGA or CPLD.

So I wasn't thinking in terms of reducing chips. I was thinking in terms of reducing gates. This is particularly important if you're actually going to be programming FPGAs or CPLDs.

 

[Kenneth Mann]

Recheck your assumptions.

This is intriguing. Like with the others, a K-Map shows that this is in minimal form as it has been stated to us. The question, however is, "is there anything else? Has anything else been left out? In particular, are there any additional 'Don't care' conditions? These can be important if there are any."

[ BTW: I'm sorry that I've been away from the forum for so long, however I ran into problems switching from a dial-up access to DSL. It was just one problem after another; including even an apparent mother board failure. ]

KM