Random89 said:
I have got the course text suggested but it is one of those books which is not easy to comprehend with no knowledge of the subject. I have tried talking to the lecturer but he just keeps suggesting the course texts. I was just hoping someone here had some experience of books or sites they have used that explains it fully (as in how they work) and not just what they do.
I'd suggest that instead of trying to find a full explanation, that you instead look for a simplified model, and then build up your understanding as you pick up transistor theory (second semester course? third year?) A high level explanation may be more suited, especially if you don't have any / much experience (in other courses) with even BJTs. If it may seem that they've gone over a disproportionate amount of material, that's probably because they glossed over a lot of the (low-level) details, which is what you'd expect for a (introductory digital) course. Once you've got this high-level understanding down, you can start delving downwards. Unless you guys have already done standard circuit analysis and covered transistor operation in other courses.
It may seem daunting when presented with circuits involving 2, 3, 4+ transistors, but the key is to simplify the functionality to on or off states (the whole digital paradigm). Thus, when you have an NPN (BJT arrow Not Pointed iN--my memory technique) and the base receives a '1' (possibly 5V through a resistor) it's on, and you pretend that the collector-emitter are connected together (with no connection to the base--this isn't true but is functionally correct for this first-level analysis). The same thing happens when a PNP (BJT arrow Pointed iN Polarity) has a '0' applied to its base.
When the opposite of these apply (a '0' to an NPN base, '1' to a PNP) make the simplification that the Collector and Emitter are disconnected (and that, again, neither of these are connected to the base).
When the output stage of a logic circuit contains a PNP and an NPN with the collectors tied together, or one NPN pulling low (output gets connected to ground when on) and one NPN pulling high (output gets connected to 5V, Vcc, or '1' when on), this is known as a totem pole output, because the amount of current that can be supplied or sunk from the output is (roughly) the same (when properly designed--neglecting device specifics). This is as opposed to an open collector configuration, or an open collector with a pull-up resistor attached to the output.
I hope this helps. But here's a (very) high-level intro that doesn't require transistor analysis, and also goes over other varieties of logic:
http://www.asic-world.com/digital/gates5.html