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Digital Logic - Timing Analysis

  1. Dec 9, 2007 #1


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    What do they mean by saying that " If the clock frequency is 45MHz and we use 50MHz then the circuit will not work".

    I am confused :uhh: I donot understand the timing analysis in digital logic.

    Please help me out

  2. jcsd
  3. Dec 9, 2007 #2


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  4. Dec 20, 2009 #3
    The circuit in the link provided should answer your question completely: http://www.teahlab.com/multivibrators/jkflipflopv01/JKflipflopV01.html
    When J = K = 1, flipping the Clock signal should cause the flipflop to toggle, but because of the timing signal it won't.
    To see how the circuit is actually supposed to work, set J = K = C = 1 then continuously click somewhere else on the board to witness the toggle action.

    I hope this help. If you have more questions let me know.
  5. Dec 20, 2009 #4


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    Staff: Mentor

  6. Dec 23, 2009 #5


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    45 MHz is near the upper limit of some integrated circuits.

    Counters in the 74HC family of chips stop working at about 45 MHz so you could get an individual chip that will count 45 MHz pulses but will not count 50 MHz properly, or at all.

    Another reason 50 MHz might not be suitable is that simple counters divide by some fixed integer quantity. They may divide by 10 to give 4.5 MHz from 45 MHz, for example.
    If you clocked such a chip with a 50 MHz signal, the output would be 5.0 MHz and this may not be useful because you want 4.5 MHz.

    You would need to ask about how the chip was being used, and what sort of chip it was.
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