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Dynamic RAM: Capacitance and Refreshing

  1. Sep 22, 2016 #1
    Wes thu hal,

    I have been researching computer hardware aspects, and I have been recently looking at RAM types, particularly DRAM. I am think of making a simple model of it for a hobby.

    For a DRAM bit cell, does the capacitance value matter? What affects does it have if it is big or small, e.g. 1pF or 200uF?

    Also, I read that DRAM needs to refresh each cell, because even when the transistor's gate is not conducting, the capacitor still can leak charge. In addition, I read that it is recommended that it is refreshed every 50 or 100ms. Is this a necessity for large capacitors, since a refreshing system is quite complex. I have ran several simulations of DRAM cells with large capacitor values, and they do not seem to discharge. Are the simulators inaccurate for this?

    Thanks in advance,
  2. jcsd
  3. Sep 22, 2016 #2


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    hi there LtIvan

    in any typical DRAM chip such large capacitance values are impossible to obtain. The physical size of a non-SMD 1uF to 100uF value capacitor is many times bigger than the whole DRAM chip die. Even a 1pF capacitor is huge in comparison.

    typical capacitance values in a DRAM bit cell are around 30 fF ( femtoFarads = equal to 10−15 Farads)

  4. Sep 22, 2016 #3
    Briefly, the whole point of DRAM is that it's cheap. DRAM can be tightly packed on to chips. That offsets the performance penalties of having to refresh it. All you need to do in order to make DRAM into SRAM is add a few more transistors for each cell. Then you don't have to do the refreshing. If you're capacitors become as large as the the extra transistors would be then you simply have created an expensive DRAM.
  5. Sep 23, 2016 #4
    However, the main question I am asking, hypothetically, if I had DRAM cell with a large capacitance, does it need to be refreshed.

    Thanks in advance,
  6. Sep 23, 2016 #5


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  7. Sep 29, 2016 #6
    There appears to be a problem when I was observing simulations of a DRAM cell in LTSpice IV.
    The figure attached shows the circuit.
    The circuit is an array of four DRAM cells in a two by two array. Each cell is a composition of a capacitor at 220μF and a N channel MOSFET.
    Node 002 is at the positive end of C1, node 003 is the positive of C2, node 007 is the positive of C3 and node 008 is the positive of C4.

    When the first wordline, V1, is high, 1 bit, at +1V, and the first bitline, V3, is high too, 1 bit, at +1V, the others low, C1 should be charged and the rest discharged. However, when the model is ran C1 and C3 are both charged. In the figure, both node 002 and 007 are at +1V. Before the test, all capacitors were discharged when both wordlines and bitlines low at 0V. May it be something wrong with the transistors? I suspect they are the wrong type of transistor, because a DRAM cell requires a standard FET?

    If I am doing something incorrect or invalid please point out and explain.

    Thanks in advance,

    Attached Files:

    • sim.png
      File size:
      66.1 KB
  8. Oct 19, 2016 #7
    firstly, capacitors in DRAM cell not only leak, sometimes they also Charge by a mistake. so refresh means that some Caps need to be zeroed down to 0v , some maxed up +3.3v. you must have a voltage level detector in there. if after 70 or so microseconds a Cap voltage is below central threshold (1.65V) it means it was holding 0v and charged up errorously,so you must discharge it back to 0v during the refresh process. if Cap voltage level is beyond central threshold it means it was originally holding 3.3v but got discharged so you must recharge it up to 3.3v . main goal is to guarantee that Caps will hold their voltage levels below, or above central threshold for 70 or more microseconds. if that rule is violated threshold voltage level detector will make a mistake and legal voltage level never be recovered. will be lost, (overwritten by the second voltage level).
    Last edited: Oct 19, 2016
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