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Need help analyzing and audio amplifier [final exam study guide]

  1. Dec 7, 2013 #1
    1. The problem statement, all variables and given/known data
    bS7Lois.png


    2. Relevant equations
    See Image


    3. The attempt at a solution

    I am confused where to start this problem. Obviously i need to get at the DC load line for Q1. But the problem is that I was taught in class that the DC load lines intercepts for a transistor are x-intercept Vcc and y-intercept Vcc/(Re+Rc). But Q1 has no Re OR Rc! So how am i supposed to find its y-intercept?!

    Secondly I don't exactly know what open-loop voltage gain is, what is "open-loop" referring to? The voltage gain without the feedback loop? I am just unsure how to analyze the circuit like this?

    Lastly, is by "closed loop gain" do they just mean the overall gain of this exact circuit?

    Any help in guiding me through part a, b or c would be greatly appreciated!
     
    Last edited: Dec 7, 2013
  2. jcsd
  3. Dec 8, 2013 #2

    gneill

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    Staff: Mentor

    Hi BenBa, Welcome to Physics Forums.

    Suppose Q1 is ON and near saturation. What will Q2 be doing under those conditions? What is the current path for Q1's Ic? Is there more than one path?

    Yes, it's the voltage gain without the feedback path.

    Yes.

    Looks like you've got the gist of it.
     
  4. Dec 9, 2013 #3
    When Q1 is on an near saturation? Well aren't they in push-pull configuration? So whenever Q1 is ever on Q2 is off, i dont know what Q1 being near saturation entails...
     
  5. Dec 9, 2013 #4

    gneill

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    Yes, Q1 being on implies Q2 being off. So that eliminates one current path. Being near saturation implies that the transistor is as "on" as it can be. Now it could be that the overall circuit precludes the transistors being driven to saturation, but we're looking at the load line here, which has as its intercepts the extreme possibilities.

    If the given transistor (BD139) is saturated, what's its collector-emitter voltage? That should tell you what the maximum possible potential is at the emitter...
     
  6. Dec 9, 2013 #5
    the collector emitter drop when Q1 is "as on as possible" is simply Vbe (Which is standard 0.7volts), right?

    I think i just realized that the y intercept is at VCC/R4 because R4 is acting as the emitter resistor.

    But why can we assume the transistor is "as on as possible"? Isn't the Q point somewhere in between?
     
  7. Dec 9, 2013 #6

    gneill

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    Nope. But it will be in that neighborhood. Look up the characteristics of the transistor.

    Is R4 the ONLY path for the emitter current?

    Yes, the operating point lies along the load line (usually somewhere in the middle). But the end points of the load line represent the extreme possibilities of circuit operation. They occur at saturation and cutoff.
     
  8. Dec 9, 2013 #7
    What characteristic of the transistor do i need to look at, our professor has never asked us to do that when the transistor is "as on as possible" so it it okay to assume it is essentially just 0.7?

    Since this is DC analysis don't you cut off the Cout, so for the y intercept isn't the only place for the DC current to go through R4?
     
  9. Dec 9, 2013 #8

    gneill

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    Do a web search on "BD139 datasheet". You're looking for VCE(sat). You should be able to locate the Fairchild Semiconductor datasheet PDF.

    Yes, Cout will be an "open" to DC. But is there anything else connected to the top of R4?
     
  10. Dec 9, 2013 #9
    Ah the feedback!

    That looks so complicated though, i have no idea how to approach that because it feeds back into the op amp which then feeds back into the transistor..
     
  11. Dec 9, 2013 #10

    gneill

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    What's the DC potential where the feedback resistor terminates?
     
  12. Dec 9, 2013 #11
    zero, because of the ideal op amp.
     
  13. Dec 9, 2013 #12
    so the current splits between R4 in paraallel with R2 which is in parallel with C1, this is complicated
     
  14. Dec 9, 2013 #13

    gneill

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    Yes!

    Is C1 relevant for DC?
     
  15. Dec 9, 2013 #14
    Gotcha! So the voltage is Vcc-Vsat-0.7 and there are two paths, but the current splits between R4 and R2. But we still don't know how much current is going out of the push-pull, right?
     
  16. Dec 9, 2013 #15

    gneill

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    VCE(sat) is the only potential drop of interest between the source +Vcc and the emitter (top of R4). It's the collector-emitter voltage.

    If you know the potential at the top of R4 / R2 you can find the total current. Q2 is cut off, so no current there...

    As you've already stated, R4 and R2 are essentially in parallel and thus comprise your RE...
     
  17. Dec 9, 2013 #16
    So current out of the push-pull is equal to [Vcc-Vce(sat)]/[R4||R2] I get it!

    But is this current also the same as the collector current for the Q point?
     
  18. Dec 9, 2013 #17

    gneill

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    No, this just establishes one end of the load line (for part (a) of the problem). The operating point will lie somewhere along that line. What conditions are usually applied to establish the operating point?
     
  19. Dec 9, 2013 #18
    So that i the y-intercept then? And we know our x-intercept is simply Vcc, right?

    usually to establish the operating point after we know our intercepts we can write the equation [itex] i = \frac{-1}{R2||R4}Vce+\frac{Vcc-Vce(sat)}{R4||R2}[/itex]

    But we know neither the operating current or the operating Vce so we cant just plug one in to get the other, do we assume that Vce is in the middle of the x axis (Vcc/2) for maximum symmetric swing? Or can we not simply do that?
     
    Last edited: Dec 9, 2013
  20. Dec 9, 2013 #19

    gneill

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    For the load line y-intercept I just realized that you want to exclude the transistor from consideration (sorry about the Vsat digression, but at least it achieved the determination of the effective RE). The y-intercept will just be Vcc/RE since there's no RC to add to it. It's the current that would result if the transistor were a perfect switch with zero VCE.

    The quiescent operating point occurs when the input signal to the overall amplifier is zero (assuming that the input would be a signal centered around zero). What current would you expect in the transistors when the input is zero?
     
  21. Dec 9, 2013 #20
    Can you explain this a little more, did I make a mistake? Is our y-intercept still Vcc/[R4||R2]?

    The current in both transistors should be zero if input is zero right? Aren't both off when the Vin to the push-pull is zero? Or are they both on?
     
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